Commit 3a35093a authored by Joakim Zhang's avatar Joakim Zhang Committed by Arnaldo Carvalho de Melo
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perf vendor events arm64: Add JSON metrics for imx8mq DDR Perf 



Add JSON metrics for imx8mq DDR Perf.

Signed-off-by: default avatarJoakim Zhang <qiangqing.zhang@nxp.com>
Reviewed-by: default avatarJohn Garry <john.garry@huawei.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de> <s.hauer@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-imx@nxp.com
Cc: kernel@pengutronix.de
Link: https://lore.kernel.org/r/20210127105734.12198-4-qiangqing.zhang@nxp.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 842ed298

tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/ddrc.json

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[

   {

           "BriefDescription": "ddr cycles event",

           "EventCode": "0x00",

           "EventName": "imx8mq_ddr.cycles",

           "Unit": "imx8_ddr",

           "Compat": "i.MX8MQ"

   },

   {

           "BriefDescription": "ddr read-cycles event",

           "EventCode": "0x2a",

           "EventName": "imx8mq_ddr.read_cycles",

           "Unit": "imx8_ddr",

           "Compat": "i.MX8MQ"

   },

   {

           "BriefDescription": "ddr write-cycles event",

           "EventCode": "0x2b",

           "EventName": "imx8mq_ddr.write_cycles",

           "Unit": "imx8_ddr",

           "Compat": "i.MX8MQ"

   },

   {

           "BriefDescription": "ddr read event",

           "EventCode": "0x35",

           "EventName": "imx8mq_ddr.read",

           "Unit": "imx8_ddr",

           "Compat": "i.MX8MQ"

   },

   {

           "BriefDescription": "ddr write event",

           "EventCode": "0x38",

           "EventName": "imx8mq_ddr.write",

           "Unit": "imx8_ddr",

           "Compat": "i.MX8MQ"

   }

]

tools/perf/pmu-events/arch/arm64/freescale/imx8mq/sys/metrics.json

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[

   {

	    "BriefDescription": "bytes all masters read from ddr based on read-cycles event",

	    "MetricName": "imx8mq_ddr_read.all",

	    "MetricExpr": "imx8mq_ddr.read_cycles * 4 * 4",

	    "ScaleUnit": "9.765625e-4KB",

	    "Unit": "imx8_ddr",

	    "Compat": "i.MX8MQ"

   },

   {

	    "BriefDescription": "bytes all masters write to ddr based on write-cycles event",

	    "MetricName": "imx8mq_ddr_write.all",

	    "MetricExpr": "imx8mq_ddr.write_cycles * 4 * 4",

	    "ScaleUnit": "9.765625e-4KB",

	    "Unit": "imx8_ddr",

	    "Compat": "i.MX8MQ"

    }

]