Commit 3a03eb79 authored by Andrew Vasquez's avatar Andrew Vasquez Committed by James Bottomley
Browse files

[SCSI] qla2xxx: Add ISP81XX support. 



Codes to support new FCoE boards.

Signed-off-by: default avatarAndrew Vasquez <andrew.vasquez@qlogic.com>
Signed-off-by: default avatarJames Bottomley <James.Bottomley@HansenPartnership.com>
parent 444786d7

drivers/scsi/qla2xxx/qla_attr.c

+24 −2
Original line number Diff line number Diff line
@@ -303,7 +303,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, 
		else if (start == (ha->flt_region_boot * 4) ||

		    start == (ha->flt_region_fw * 4))

			valid = 1;

		else if (IS_QLA25XX(ha) &&

		else if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) &&

		    start == (ha->flt_region_vpd_nvram * 4))

		    valid = 1;

		if (!valid) {
@@ -815,6 +815,21 @@ qla2x00_total_isp_aborts_show(struct device *dev, 
	    ha->qla_stats.total_isp_aborts);

}



static ssize_t

qla2x00_mpi_version_show(struct device *dev, struct device_attribute *attr,

    char *buf)

{

	scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));

	struct qla_hw_data *ha = vha->hw;



	if (!IS_QLA81XX(ha))

		return snprintf(buf, PAGE_SIZE, "\n");



	return snprintf(buf, PAGE_SIZE, "%02x.%02x.%02x.%02x (%x)\n",

	    ha->mpi_version[0], ha->mpi_version[1], ha->mpi_version[2],

	    ha->mpi_version[3], ha->mpi_capabilities);

}



static DEVICE_ATTR(driver_version, S_IRUGO, qla2x00_drvr_version_show, NULL);

static DEVICE_ATTR(fw_version, S_IRUGO, qla2x00_fw_version_show, NULL);

static DEVICE_ATTR(serial_num, S_IRUGO, qla2x00_serial_num_show, NULL);
@@ -839,6 +854,7 @@ static DEVICE_ATTR(optrom_fw_version, S_IRUGO, qla2x00_optrom_fw_version_show, 
		   NULL);

static DEVICE_ATTR(total_isp_aborts, S_IRUGO, qla2x00_total_isp_aborts_show,

		   NULL);

static DEVICE_ATTR(mpi_version, S_IRUGO, qla2x00_mpi_version_show, NULL);



struct device_attribute *qla2x00_host_attrs[] = {

	&dev_attr_driver_version,
@@ -858,6 +874,7 @@ struct device_attribute *qla2x00_host_attrs[] = { 
	&dev_attr_optrom_fcode_version,

	&dev_attr_optrom_fw_version,

	&dev_attr_total_isp_aborts,

	&dev_attr_mpi_version,

	NULL,

};
@@ -892,6 +909,9 @@ qla2x00_get_host_speed(struct Scsi_Host *shost) 
	case PORT_SPEED_8GB:

		speed = FC_PORTSPEED_8GBIT;

		break;

	case PORT_SPEED_10GB:

		speed = FC_PORTSPEED_10GBIT;

		break;

	}

	fc_host_speed(shost) = speed;

}
@@ -1382,7 +1402,9 @@ qla2x00_init_host_attr(scsi_qla_host_t *vha) 
	fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports;

	fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count;



	if (IS_QLA25XX(ha))

	if (IS_QLA81XX(ha))

		speed = FC_PORTSPEED_10GBIT;

	else if (IS_QLA25XX(ha))

		speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT |

		    FC_PORTSPEED_2GBIT | FC_PORTSPEED_1GBIT;

	else if (IS_QLA24XX_TYPE(ha))

drivers/scsi/qla2xxx/qla_dbg.c

+324 −0
Original line number Diff line number Diff line
@@ -1324,6 +1324,330 @@ qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 
	if (!hardware_locked)

		spin_unlock_irqrestore(&ha->hardware_lock, flags);

}



void

qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)

{

	int		rval;

	uint32_t	cnt;

	uint32_t	risc_address;

	struct qla_hw_data *ha = vha->hw;

	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;

	uint32_t __iomem *dmp_reg;

	uint32_t	*iter_reg;

	uint16_t __iomem *mbx_reg;

	unsigned long	flags;

	struct qla81xx_fw_dump *fw;

	uint32_t	ext_mem_cnt;

	void		*nxt, *nxt_chain;

	uint32_t	*last_chain = NULL;

	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);



	risc_address = ext_mem_cnt = 0;

	flags = 0;



	if (!hardware_locked)

		spin_lock_irqsave(&ha->hardware_lock, flags);



	if (!ha->fw_dump) {

		qla_printk(KERN_WARNING, ha,

		    "No buffer available for dump!!!\n");

		goto qla81xx_fw_dump_failed;

	}



	if (ha->fw_dumped) {

		qla_printk(KERN_WARNING, ha,

		    "Firmware has been previously dumped (%p) -- ignoring "

		    "request...\n", ha->fw_dump);

		goto qla81xx_fw_dump_failed;

	}

	fw = &ha->fw_dump->isp.isp81;

	qla2xxx_prep_dump(ha, ha->fw_dump);



	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));



	/* Pause RISC. */

	rval = qla24xx_pause_risc(reg);

	if (rval != QLA_SUCCESS)

		goto qla81xx_fw_dump_failed_0;



	/* Host/Risc registers. */

	iter_reg = fw->host_risc_reg;

	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);

	qla24xx_read_window(reg, 0x7010, 16, iter_reg);



	/* PCIe registers. */

	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);

	RD_REG_DWORD(&reg->iobase_addr);

	WRT_REG_DWORD(&reg->iobase_window, 0x01);

	dmp_reg = &reg->iobase_c4;

	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));

	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));

	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));

	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));



	WRT_REG_DWORD(&reg->iobase_window, 0x00);

	RD_REG_DWORD(&reg->iobase_window);



	/* Host interface registers. */

	dmp_reg = &reg->flash_addr;

	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)

		fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));



	/* Disable interrupts. */

	WRT_REG_DWORD(&reg->ictrl, 0);

	RD_REG_DWORD(&reg->ictrl);



	/* Shadow registers. */

	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);

	RD_REG_DWORD(&reg->iobase_addr);

	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);

	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);

	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);

	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);

	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);

	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);

	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);

	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);

	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);

	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);

	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);

	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));



	/* RISC I/O register. */

	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);

	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));



	/* Mailbox registers. */

	mbx_reg = &reg->mailbox0;

	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)

		fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));



	/* Transfer sequence registers. */

	iter_reg = fw->xseq_gp_reg;

	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);

	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);



	iter_reg = fw->xseq_0_reg;

	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);

	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);



	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);



	/* Receive sequence registers. */

	iter_reg = fw->rseq_gp_reg;

	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);

	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);



	iter_reg = fw->rseq_0_reg;

	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);

	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);



	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);

	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);



	/* Auxiliary sequence registers. */

	iter_reg = fw->aseq_gp_reg;

	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);

	qla24xx_read_window(reg, 0xB070, 16, iter_reg);



	iter_reg = fw->aseq_0_reg;

	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);

	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);



	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);

	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);



	/* Command DMA registers. */

	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);



	/* Queues. */

	iter_reg = fw->req0_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);

	dmp_reg = &reg->iobase_q;

	for (cnt = 0; cnt < 7; cnt++)

		*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));



	iter_reg = fw->resp0_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);

	dmp_reg = &reg->iobase_q;

	for (cnt = 0; cnt < 7; cnt++)

		*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));



	iter_reg = fw->req1_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);

	dmp_reg = &reg->iobase_q;

	for (cnt = 0; cnt < 7; cnt++)

		*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));



	/* Transmit DMA registers. */

	iter_reg = fw->xmt0_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);

	qla24xx_read_window(reg, 0x7610, 16, iter_reg);



	iter_reg = fw->xmt1_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);

	qla24xx_read_window(reg, 0x7630, 16, iter_reg);



	iter_reg = fw->xmt2_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);

	qla24xx_read_window(reg, 0x7650, 16, iter_reg);



	iter_reg = fw->xmt3_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);

	qla24xx_read_window(reg, 0x7670, 16, iter_reg);



	iter_reg = fw->xmt4_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);

	qla24xx_read_window(reg, 0x7690, 16, iter_reg);



	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);



	/* Receive DMA registers. */

	iter_reg = fw->rcvt0_data_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);

	qla24xx_read_window(reg, 0x7710, 16, iter_reg);



	iter_reg = fw->rcvt1_data_dma_reg;

	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);

	qla24xx_read_window(reg, 0x7730, 16, iter_reg);



	/* RISC registers. */

	iter_reg = fw->risc_gp_reg;

	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);

	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);



	/* Local memory controller registers. */

	iter_reg = fw->lmc_reg;

	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);

	qla24xx_read_window(reg, 0x3070, 16, iter_reg);



	/* Fibre Protocol Module registers. */

	iter_reg = fw->fpm_hdw_reg;

	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);

	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);



	/* Frame Buffer registers. */

	iter_reg = fw->fb_hdw_reg;

	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);

	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);

	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);



	/* Multi queue registers */

	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,

	    &last_chain);



	rval = qla24xx_soft_reset(ha);

	if (rval != QLA_SUCCESS)

		goto qla81xx_fw_dump_failed_0;



	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),

	    &nxt);

	if (rval != QLA_SUCCESS)

		goto qla81xx_fw_dump_failed_0;



	nxt = qla2xxx_copy_queues(ha, nxt);



	nxt = qla24xx_copy_eft(ha, nxt);



	/* Chain entries -- started with MQ. */

	qla25xx_copy_fce(ha, nxt_chain, &last_chain);

	if (last_chain) {

		ha->fw_dump->version |= __constant_htonl(DUMP_CHAIN_VARIANT);

		*last_chain |= __constant_htonl(DUMP_CHAIN_LAST);

	}



qla81xx_fw_dump_failed_0:

	if (rval != QLA_SUCCESS) {

		qla_printk(KERN_WARNING, ha,

		    "Failed to dump firmware (%x)!!!\n", rval);

		ha->fw_dumped = 0;



	} else {

		qla_printk(KERN_INFO, ha,

		    "Firmware dump saved to temp buffer (%ld/%p).\n",

		    base_vha->host_no, ha->fw_dump);

		ha->fw_dumped = 1;

	}



qla81xx_fw_dump_failed:

	if (!hardware_locked)

		spin_unlock_irqrestore(&ha->hardware_lock, flags);

}



/****************************************************************************/

/*                         Driver Debug Functions.                          */

/****************************************************************************/

drivers/scsi/qla2xxx/qla_dbg.h

+40 −0
Original line number Diff line number Diff line
@@ -251,6 +251,45 @@ struct qla25xx_fw_dump { 
	uint32_t ext_mem[1];

};



struct qla81xx_fw_dump {

	uint32_t host_status;

	uint32_t host_risc_reg[32];

	uint32_t pcie_regs[4];

	uint32_t host_reg[32];

	uint32_t shadow_reg[11];

	uint32_t risc_io_reg;

	uint16_t mailbox_reg[32];

	uint32_t xseq_gp_reg[128];

	uint32_t xseq_0_reg[48];

	uint32_t xseq_1_reg[16];

	uint32_t rseq_gp_reg[128];

	uint32_t rseq_0_reg[32];

	uint32_t rseq_1_reg[16];

	uint32_t rseq_2_reg[16];

	uint32_t aseq_gp_reg[128];

	uint32_t aseq_0_reg[32];

	uint32_t aseq_1_reg[16];

	uint32_t aseq_2_reg[16];

	uint32_t cmd_dma_reg[16];

	uint32_t req0_dma_reg[15];

	uint32_t resp0_dma_reg[15];

	uint32_t req1_dma_reg[15];

	uint32_t xmt0_dma_reg[32];

	uint32_t xmt1_dma_reg[32];

	uint32_t xmt2_dma_reg[32];

	uint32_t xmt3_dma_reg[32];

	uint32_t xmt4_dma_reg[32];

	uint32_t xmt_data_dma_reg[16];

	uint32_t rcvt0_data_dma_reg[32];

	uint32_t rcvt1_data_dma_reg[32];

	uint32_t risc_gp_reg[128];

	uint32_t lmc_reg[128];

	uint32_t fpm_hdw_reg[224];

	uint32_t fb_hdw_reg[208];

	uint32_t code_ram[0x2000];

	uint32_t ext_mem[1];

};



#define EFT_NUM_BUFFERS		4

#define EFT_BYTES_PER_BUFFER	0x4000

#define EFT_SIZE		((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
@@ -313,5 +352,6 @@ struct qla2xxx_fw_dump { 
		struct qla2300_fw_dump isp23;

		struct qla24xx_fw_dump isp24;

		struct qla25xx_fw_dump isp25;

		struct qla81xx_fw_dump isp81;

	} isp;

};

drivers/scsi/qla2xxx/qla_def.h

+18 −3
Original line number Diff line number Diff line
@@ -2303,6 +2303,7 @@ struct qla_hw_data { 
#define PORT_SPEED_2GB  0x01

#define PORT_SPEED_4GB  0x03

#define PORT_SPEED_8GB  0x04

#define PORT_SPEED_10GB	0x13

	uint16_t	link_data_rate;         /* F/W operating speed */



	uint8_t		current_topology;
@@ -2322,6 +2323,7 @@ struct qla_hw_data { 


#define PCI_DEVICE_ID_QLOGIC_ISP2532    0x2532

#define PCI_DEVICE_ID_QLOGIC_ISP8432    0x8432

#define PCI_DEVICE_ID_QLOGIC_ISP8001	0x8001

	uint32_t	device_type;

#define DT_ISP2100                      BIT_0

#define DT_ISP2200                      BIT_1
@@ -2336,7 +2338,8 @@ struct qla_hw_data { 
#define DT_ISP5432                      BIT_10

#define DT_ISP2532                      BIT_11

#define DT_ISP8432                      BIT_12

#define DT_ISP_LAST                     (DT_ISP8432 << 1)

#define DT_ISP8001			BIT_13

#define DT_ISP_LAST			(DT_ISP8001 << 1)



#define DT_IIDMA                        BIT_26

#define DT_FWI2                         BIT_27
@@ -2358,6 +2361,7 @@ struct qla_hw_data { 
#define IS_QLA5432(ha)  (DT_MASK(ha) & DT_ISP5432)

#define IS_QLA2532(ha)  (DT_MASK(ha) & DT_ISP2532)

#define IS_QLA8432(ha)  (DT_MASK(ha) & DT_ISP8432)

#define IS_QLA8001(ha)	(DT_MASK(ha) & DT_ISP8001)



#define IS_QLA23XX(ha)  (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \

			IS_QLA6312(ha) || IS_QLA6322(ha))
@@ -2367,9 +2371,10 @@ struct qla_hw_data { 
#define IS_QLA84XX(ha)  (IS_QLA8432(ha))

#define IS_QLA24XX_TYPE(ha)     (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \

				IS_QLA84XX(ha))

#define IS_QLA81XX(ha)		(IS_QLA8001(ha))

#define IS_QLA2XXX_MIDTYPE(ha)	(IS_QLA24XX(ha) || IS_QLA84XX(ha) || \

				IS_QLA25XX(ha))

#define IS_NOPOLLING_TYPE(ha)	(IS_QLA25XX(ha) && \

				IS_QLA25XX(ha) || IS_QLA81XX(ha))

#define IS_NOPOLLING_TYPE(ha)	((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \

				(ha)->flags.msix_enabled)



#define IS_IIDMA_CAPABLE(ha)    ((ha)->device_type & DT_IIDMA)
@@ -2468,6 +2473,9 @@ struct qla_hw_data { 
	uint8_t		fw_seriallink_options[4];

	uint16_t	fw_seriallink_options24[4];



	uint8_t		mpi_version[4];

	uint32_t	mpi_capabilities;



	/* Firmware dump information. */

	struct qla2xxx_fw_dump *fw_dump;

	uint32_t	fw_dump_len;
@@ -2515,6 +2523,12 @@ struct qla_hw_data { 
	uint8_t 	fcode_revision[16];

	uint32_t	fw_revision[4];



	/* Offsets for flash/nvram access (set to ~0 if not used). */

	uint32_t	flash_conf_off;

	uint32_t	flash_data_off;

	uint32_t	nvram_conf_off;

	uint32_t	nvram_data_off;



	uint32_t	fdt_wrt_disable;

	uint32_t	fdt_erase_cmd;

	uint32_t	fdt_block_size;
@@ -2729,6 +2743,7 @@ typedef struct scsi_qla_host { 
#define OPTROM_SIZE_2322	0x100000

#define OPTROM_SIZE_24XX	0x100000

#define OPTROM_SIZE_25XX	0x200000

#define OPTROM_SIZE_81XX	0x400000



#include "qla_gbl.h"

#include "qla_dbg.h"

drivers/scsi/qla2xxx/qla_dfs.c

+2 −1
Original line number Diff line number Diff line
@@ -113,7 +113,8 @@ int 
qla2x00_dfs_setup(scsi_qla_host_t *vha)

{

	struct qla_hw_data *ha = vha->hw;

	if (!IS_QLA25XX(ha))



	if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))

		goto out;

	if (!ha->fce)

		goto out;