Commit 39fdb65f authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64: errata: Add Cortex-A510 to the repeat tlbi list 



Cortex-A510 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.

Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent a111daf0

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -102,6 +102,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

arch/arm64/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -821,6 +821,23 @@ config ARM64_ERRATUM_2224489 


	  If unsure, say Y.



config ARM64_ERRATUM_2441009

	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI"

	default y

	select ARM64_WORKAROUND_REPEAT_TLBI

	help

	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.



	  Under very rare circumstances, affected Cortex-A510 CPUs

	  may not handle a race between a break-before-make sequence on one

	  CPU, and another CPU accessing the same page. This could allow a

	  store to a page that has been unmapped.



	  Work around this by adding the affected CPUs to the list that needs

	  TLB sequences to be done twice.



	  If unsure, say Y.



config ARM64_ERRATUM_2064142

	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"

	depends on CORESIGHT_TRBE

arch/arm64/kernel/cpu_errata.c

+7 −1
Original line number Diff line number Diff line
@@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = { 
		/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */

		ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_2441009

	{

		/* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */

		ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),

	},

#endif

	{},

};
@@ -480,7 +486,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
#endif

#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI

	{

		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807",

		.desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",

		.capability = ARM64_WORKAROUND_REPEAT_TLBI,

		.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,

		.matches = cpucap_multi_entry_cap_matches,