Commit 39f69212 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Palmer Dabbelt:

 - A fix for FPU probing in XIP kernels

 - Always enable the alternative framework for non-XIP kernels

* tag 'riscv-for-linus-6.3-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  RISC-V: always select RISCV_ALTERNATIVE for non-xip kernels
  RISC-V: add non-alternative fallback for riscv_has_extension_[un]likely()
parents 52f19595 4622f159

arch/riscv/Kconfig

+6 −6
Original line number Diff line number Diff line
@@ -126,6 +126,7 @@ config RISCV 
	select OF_IRQ

	select PCI_DOMAINS_GENERIC if PCI

	select PCI_MSI if PCI

	select RISCV_ALTERNATIVE if !XIP_KERNEL

	select RISCV_INTC

	select RISCV_TIMER if RISCV_SBI

	select SIFIVE_PLIC
@@ -401,9 +402,8 @@ config RISCV_ISA_C 
config RISCV_ISA_SVPBMT

	bool "SVPBMT extension support"

	depends on 64BIT && MMU

	depends on !XIP_KERNEL

	depends on RISCV_ALTERNATIVE

	default y

	select RISCV_ALTERNATIVE

	help

	   Adds support to dynamically detect the presence of the SVPBMT

	   ISA-extension (Supervisor-mode: page-based memory types) and
@@ -428,8 +428,8 @@ config TOOLCHAIN_HAS_ZBB 
config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on !XIP_KERNEL && MMU

	select RISCV_ALTERNATIVE

	depends on MMU

	depends on RISCV_ALTERNATIVE

	default y

	help

	   Adds support to dynamically detect the presence of the ZBB
@@ -443,9 +443,9 @@ config RISCV_ISA_ZBB 


config RISCV_ISA_ZICBOM

	bool "Zicbom extension support for non-coherent DMA operation"

	depends on !XIP_KERNEL && MMU

	depends on MMU

	depends on RISCV_ALTERNATIVE

	default y

	select RISCV_ALTERNATIVE

	select RISCV_DMA_NONCOHERENT

	help

	   Adds support to dynamically detect the presence of the ZICBOM

arch/riscv/Kconfig.erratas

+2 −4
Original line number Diff line number Diff line
@@ -2,8 +2,7 @@ menu "CPU errata selection" 


config ERRATA_SIFIVE

	bool "SiFive errata"

	depends on !XIP_KERNEL

	select RISCV_ALTERNATIVE

	depends on RISCV_ALTERNATIVE

	help

	  All SiFive errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all SiFive errata. Please say "Y"
@@ -35,8 +34,7 @@ config ERRATA_SIFIVE_CIP_1200 


config ERRATA_THEAD

	bool "T-HEAD errata"

	depends on !XIP_KERNEL

	select RISCV_ALTERNATIVE

	depends on RISCV_ALTERNATIVE

	help

	  All T-HEAD errata Kconfig depend on this Kconfig. Disabling

	  this Kconfig will disable all T-HEAD errata. Please say "Y"

arch/riscv/include/asm/hwcap.h

+30 −20
Original line number Diff line number Diff line
@@ -57,18 +57,31 @@ struct riscv_isa_ext_data { 
	unsigned int isa_ext_id;

};



unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



static __always_inline bool

riscv_has_extension_likely(const unsigned long ext)

{

	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("j	%l[l_no]", "nop", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_no);

	} else {

		if (!__riscv_isa_extension_available(NULL, ext))

			goto l_no;

	}



	return true;

l_no:
@@ -81,26 +94,23 @@ riscv_has_extension_unlikely(const unsigned long ext) 
	compiletime_assert(ext < RISCV_ISA_EXT_MAX,

			   "ext must be < RISCV_ISA_EXT_MAX");



	if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

		asm_volatile_goto(

		ALTERNATIVE("nop", "j	%l[l_yes]", 0, %[ext], 1)

		:

		: [ext] "i" (ext)

		:

		: l_yes);

	} else {

		if (__riscv_isa_extension_available(NULL, ext))

			goto l_yes;

	}



	return false;

l_yes:

	return true;

}



unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);



#define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)



bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);

#define riscv_isa_extension_available(isa_bitmap, ext)	\

	__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)



#endif



#endif /* _ASM_RISCV_HWCAP_H */