Commit 39c8bf2b authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc: Retire e200 core (mpc555x processor) 



There is no defconfig selecting CONFIG_E200, and no platform.

e200 is an earlier version of booke, a predecessor of e500,
with some particularities like an unified cache instead of both an
instruction cache and a data cache.

Remove it.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: default avatarScott Wood <oss@buserror.net>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/34ebc3ba2c768d97f363bd5f2deea2356e9ae127.1605589460.git.christophe.leroy@csgroup.eu
parent ff57698a

arch/powerpc/include/asm/cputable.h

+0 −11
Original line number Diff line number Diff line
@@ -41,7 +41,6 @@ extern int machine_check_4xx(struct pt_regs *regs); 
extern int machine_check_440A(struct pt_regs *regs);

extern int machine_check_e500mc(struct pt_regs *regs);

extern int machine_check_e500(struct pt_regs *regs);

extern int machine_check_e200(struct pt_regs *regs);

extern int machine_check_47x(struct pt_regs *regs);

int machine_check_8xx(struct pt_regs *regs);

int machine_check_83xx(struct pt_regs *regs);
@@ -381,10 +380,6 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_440x6	(CPU_FTR_NOEXECUTE | \

	    CPU_FTR_INDEXED_DCR)

#define CPU_FTRS_47X	(CPU_FTRS_440x6)

#define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \

	    CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DEBUG_LVL_EXC)

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \

	    CPU_FTR_NOEXECUTE)
@@ -529,9 +524,6 @@ enum { 
#elif defined(CONFIG_44x)

	    CPU_FTRS_44X | CPU_FTRS_440x6 |

#endif

#ifdef CONFIG_E200

	    CPU_FTRS_E200 |

#endif

#ifdef CONFIG_E500

	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |

#endif
@@ -601,9 +593,6 @@ enum { 
#elif defined(CONFIG_44x)

	    CPU_FTRS_44X & CPU_FTRS_440x6 &

#endif

#ifdef CONFIG_E200

	    CPU_FTRS_E200 &

#endif

#ifdef CONFIG_E500

	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &

#endif

arch/powerpc/include/asm/mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -171,7 +171,7 @@ enum { 
#elif defined(CONFIG_44x)

		MMU_FTR_TYPE_44x |

#endif

#if defined(CONFIG_E200) || defined(CONFIG_E500)

#ifdef CONFIG_E500

		MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | MMU_FTR_USE_TLBILX |

#endif

#ifdef CONFIG_PPC_BOOK3S_32

arch/powerpc/include/asm/reg.h

+0 −5
Original line number Diff line number Diff line
@@ -1233,14 +1233,9 @@ 
#define SPRN_SPRG_WSCRATCH_MC	SPRN_SPRG1

#define SPRN_SPRG_RSCRATCH4	SPRN_SPRG7R

#define SPRN_SPRG_WSCRATCH4	SPRN_SPRG7W

#ifdef CONFIG_E200

#define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG6R

#define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG6W

#else

#define SPRN_SPRG_RSCRATCH_DBG	SPRN_SPRG9

#define SPRN_SPRG_WSCRATCH_DBG	SPRN_SPRG9

#endif

#endif



#ifdef CONFIG_PPC_8xx

#define SPRN_SPRG_SCRATCH0	SPRN_SPRG0

arch/powerpc/include/asm/reg_booke.h

+0 −12
Original line number Diff line number Diff line
@@ -281,18 +281,6 @@ 
#define MSRP_PMMP	0x00000004 /* Protect MSR[PMM] */

#endif



#ifdef CONFIG_E200

#define MCSR_MCP 	0x80000000UL /* Machine Check Input Pin */

#define MCSR_CP_PERR 	0x20000000UL /* Cache Push Parity Error */

#define MCSR_CPERR 	0x10000000UL /* Cache Parity Error */

#define MCSR_EXCP_ERR 	0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn

					fetch for an exception handler */

#define MCSR_BUS_IRERR 	0x00000010UL /* Read Bus Error on instruction fetch*/

#define MCSR_BUS_DRERR 	0x00000008UL /* Read Bus Error on data load */

#define MCSR_BUS_WRERR 	0x00000004UL /* Write Bus Error on buffered

					store or cache line push */

#endif



/* Bit definitions for the HID1 */

#ifdef CONFIG_E500

/* e500v1/v2 */

arch/powerpc/kernel/cpu_setup_fsl_booke.S

+0 −9
Original line number Diff line number Diff line
@@ -108,15 +108,6 @@ _GLOBAL(__setup_cpu_e6500) 
#endif /* CONFIG_PPC_E500MC */



#ifdef CONFIG_PPC32

#ifdef CONFIG_E200

_GLOBAL(__setup_cpu_e200)

	/* enable dedicated debug exception handling resources (Debug APU) */

	mfspr	r3,SPRN_HID0

	ori	r3,r3,HID0_DAPUEN@l

	mtspr	SPRN_HID0,r3

	b	__setup_e200_ivors

#endif /* CONFIG_E200 */



#ifdef CONFIG_E500

#ifndef CONFIG_PPC_E500MC

_GLOBAL(__setup_cpu_e500v1)