Commit 39aee490 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add cik tile mode array query 



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0672e27b

drivers/gpu/drm/radeon/cik.c

+4 −0
Original line number Diff line number Diff line
@@ -1059,6 +1059,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
@@ -1277,6 +1278,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					gb_tile_moden = 0;

					break;

				}

				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;

				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

			}

		} else if (num_rbs < 4) {
@@ -1402,6 +1404,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
					gb_tile_moden = 0;

					break;

				}

				rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;

				WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

			}

		}
@@ -1619,6 +1622,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev) 
				gb_tile_moden = 0;

				break;

			}

			rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;

			WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);

		}

		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {

drivers/gpu/drm/radeon/radeon.h

+1 −0
Original line number Diff line number Diff line
@@ -1587,6 +1587,7 @@ struct cik_asic { 
	unsigned multi_gpu_tile_size;



	unsigned tile_config;

	uint32_t tile_mode_array[32];

};



union radeon_asic_config {

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -74,9 +74,10 @@ 
 *   2.31.0 - Add fastfb support for rs690

 *   2.32.0 - new info request for rings working

 *   2.33.0 - Add SI tiling mode array query

 *   2.34.0 - Add CIK tiling mode array query

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	33

#define KMS_DRIVER_MINOR	34

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);

drivers/gpu/drm/radeon/radeon_kms.c

+7 −7
Original line number Diff line number Diff line
@@ -423,15 +423,15 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 
		break;

	case RADEON_INFO_SI_TILE_MODE_ARRAY:

		if (rdev->family >= CHIP_BONAIRE) {

			DRM_DEBUG_KMS("tile mode array is not implemented yet\n");

			return -EINVAL;

		}

		if (rdev->family < CHIP_TAHITI) {

			DRM_DEBUG_KMS("tile mode array is si only!\n");

			return -EINVAL;

		}

			value = rdev->config.cik.tile_mode_array;

			value_size = sizeof(uint32_t)*32;

		} else if (rdev->family >= CHIP_TAHITI) {

			value = rdev->config.si.tile_mode_array;

			value_size = sizeof(uint32_t)*32;

		} else {

			DRM_DEBUG_KMS("tile mode array is si+ only!\n");

			return -EINVAL;

		}

		break;

	default:

		DRM_DEBUG_KMS("Invalid request %d\n", info->request);