Commit 397ab98e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2021-08-12' of https://gitlab.freedesktop.org/drm/msm into drm-next 



This is the main pull for v5.15, after the early pull request with
drm/scheduler conversion:

* New a6xx GPU support: a680 and 7c3
* dsi: 7nm phi, sc7280 support, test pattern generator support
* mdp4 fixes for older hw like the nexus7
* displayport fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs_tyanTeDGMH1X+Uf4wdyy7jYj-CinGXXVETiYOESahw@mail.gmail.com
parents f97a1b65 cb0927ab

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+17 −0
Original line number Diff line number Diff line
@@ -64,6 +64,18 @@ properties: 
      Indicates if the DSI controller is driving a panel which needs

      2 DSI links.



  assigned-clocks:

    minItems: 2

    maxItems: 2

    description: |

      Parents of "byte" and "pixel" for the given platform.



  assigned-clock-parents:

    minItems: 2

    maxItems: 2

    description: |

      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.



  power-domains:

    maxItems: 1
@@ -119,6 +131,8 @@ required: 
  - clock-names

  - phys

  - phy-names

  - assigned-clocks

  - assigned-clock-parents

  - power-domains

  - operating-points-v2

  - ports
@@ -159,6 +173,9 @@ examples: 
           phys = <&dsi0_phy>;

           phy-names = "dsi";



           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;

           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;



           power-domains = <&rpmhpd SC7180_CX>;

           operating-points-v2 = <&dsi_opp_table>;

Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml

0 → 100644
+72 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display DSI 7nm PHY



maintainers:

  - Jonathan Marek <jonathan@marek.ca>



allOf:

  - $ref: dsi-phy-common.yaml#



properties:

  compatible:

    oneOf:

      - const: qcom,dsi-phy-7nm

      - const: qcom,dsi-phy-7nm-8150

      - const: qcom,sc7280-dsi-phy-7nm



  reg:

    items:

      - description: dsi phy register set

      - description: dsi phy lane register set

      - description: dsi pll register set



  reg-names:

    items:

      - const: dsi_phy

      - const: dsi_phy_lane

      - const: dsi_pll



  vdds-supply:

    description: |

      Connected to VDD_A_DSI_PLL_0P9 pin (or VDDA_DSI{0,1}_PLL_0P9 for sm8150)



  phy-type:

    description: D-PHY (default) or C-PHY mode

    enum: [ 10, 11 ]

    default: 10



required:

  - compatible

  - reg

  - reg-names

  - vdds-supply



unevaluatedProperties: false



examples:

  - |

     #include <dt-bindings/clock/qcom,dispcc-sm8250.h>

     #include <dt-bindings/clock/qcom,rpmh.h>



     dsi-phy@ae94400 {

         compatible = "qcom,dsi-phy-7nm";

         reg = <0x0ae94400 0x200>,

               <0x0ae94600 0x280>,

               <0x0ae94900 0x260>;

         reg-names = "dsi_phy",

                     "dsi_phy_lane",

                     "dsi_pll";



         #clock-cells = <1>;

         #phy-cells = <0>;



         vdds-supply = <&vreg_l5a_0p88>;

         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,

                  <&rpmhcc RPMH_CXO_CLK>;

         clock-names = "iface", "ref";

     };

drivers/gpu/drm/msm/Kconfig

+3 −3
Original line number Diff line number Diff line
@@ -116,9 +116,9 @@ config DRM_MSM_DSI_10NM_PHY 
	  Choose this option if DSI PHY on SDM845 is used on the platform.



config DRM_MSM_DSI_7NM_PHY

	bool "Enable DSI 7nm PHY driver in MSM DRM (used by SM8150/SM8250)"

	bool "Enable DSI 7nm PHY driver in MSM DRM"

	depends on DRM_MSM_DSI

	default y

	help

	  Choose this option if DSI PHY on SM8150/SM8250 is used on the

	  platform.
 
	  Choose this option if DSI PHY on SM8150/SM8250/SC7280 is used on

	  the platform.

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+24 −5
Original line number Diff line number Diff line
@@ -18,6 +18,18 @@ static void a5xx_dump(struct msm_gpu *gpu); 


#define GPU_PAS_ID 13



static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);



	if (a5xx_gpu->has_whereami) {

		OUT_PKT7(ring, CP_WHERE_AM_I, 2);

		OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));

		OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));

	}

}



void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring,

		bool sync)

{
@@ -30,11 +42,8 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 
	 * Most flush operations need to issue a WHERE_AM_I opcode to sync up

	 * the rptr shadow

	 */

	if (a5xx_gpu->has_whereami && sync) {

		OUT_PKT7(ring, CP_WHERE_AM_I, 2);

		OUT_RING(ring, lower_32_bits(shadowptr(a5xx_gpu, ring)));

		OUT_RING(ring, upper_32_bits(shadowptr(a5xx_gpu, ring)));

	}

	if (sync)

		update_shadow_rptr(gpu, ring);



	spin_lock_irqsave(&ring->preempt_lock, flags);
@@ -168,6 +177,16 @@ static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 
			ibs++;

			break;

		}



		/*

		 * Periodically update shadow-wptr if needed, so that we

		 * can see partial progress of submits with large # of

		 * cmds.. otherwise we could needlessly stall waiting for

		 * ringbuffer state, simply due to looking at a shadow

		 * rptr value that has not been updated

		 */

		if ((ibs % 32) == 0)

			update_shadow_rptr(gpu, ring);

	}



	/*

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+8 −4
Original line number Diff line number Diff line
@@ -519,9 +519,9 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 
	if (!pdcptr)

		goto err;



	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

	if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))

		pdc_in_aop = true;

	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))

	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))

		pdc_address_offset = 0x30090;

	else

		pdc_address_offset = 0x30080;
@@ -933,6 +933,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) 


	/* Use a known rate to bring up the GMU */

	clk_set_rate(gmu->core_clk, 200000000);

	clk_set_rate(gmu->hub_clk, 150000000);

	ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);

	if (ret) {

		pm_runtime_put(gmu->gxpd);
@@ -1393,6 +1394,9 @@ static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) 
	gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,

		gmu->nr_clocks, "gmu");



	gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,

		gmu->nr_clocks, "hub");



	return 0;

}
@@ -1504,7 +1508,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
	 * are otherwise unused by a660.

	 */

	gmu->dummy.size = SZ_4K;

	if (adreno_is_a660(adreno_gpu)) {

	if (adreno_is_a660_family(adreno_gpu)) {

		ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);

		if (ret)

			goto err_memory;
@@ -1522,7 +1526,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
			SZ_16M - SZ_16K, 0x04000);

		if (ret)

			goto err_memory;

	} else if (adreno_is_a640(adreno_gpu)) {

	} else if (adreno_is_a640_family(adreno_gpu)) {

		ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,

			SZ_256K - SZ_16K, 0x04000);

		if (ret)