Commit 3930624c authored by Samuel Holland's avatar Samuel Holland Committed by Jernej Skrabec
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clk: sunxi-ng: d1: Limit PLL rates to stable ranges 



Set the min/max rates for audio and video PLLs to keep them from going
outside their documented stable ranges. Use the most restrictive of the
"stable" and "actual" frequencies listed in the manual.

Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220812080050.59850-1-samuel@sholland.org
parent 568035b0

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

+8 −0
Original line number Diff line number Diff line
@@ -104,6 +104,8 @@ static struct ccu_nm pll_video0_4x_clk = { 
	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),

	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */

	.min_rate	= 252000000U,

	.max_rate	= 2400000000U,

	.common		= {

		.reg		= 0x040,

		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-video0-4x", osc24M,
@@ -126,6 +128,8 @@ static struct ccu_nm pll_video1_4x_clk = { 
	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),

	.m		= _SUNXI_CCU_DIV(1, 1), /* input divider */

	.min_rate	= 252000000U,

	.max_rate	= 2400000000U,

	.common		= {

		.reg		= 0x048,

		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-video1-4x", osc24M,
@@ -175,6 +179,8 @@ static struct ccu_nm pll_audio0_4x_clk = { 
	.m		= _SUNXI_CCU_DIV(16, 6),

	.sdm		= _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),

					 0x178, BIT(31)),

	.min_rate	= 180000000U,

	.max_rate	= 3000000000U,

	.common		= {

		.reg		= 0x078,

		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,
@@ -202,6 +208,8 @@ static struct ccu_nm pll_audio1_clk = { 
	.lock		= BIT(28),

	.n		= _SUNXI_CCU_MULT_MIN(8, 8, 12),

	.m		= _SUNXI_CCU_DIV(1, 1),

	.min_rate	= 180000000U,

	.max_rate	= 3000000000U,

	.common		= {

		.reg		= 0x080,

		.hw.init	= CLK_HW_INIT_PARENTS_DATA("pll-audio1", osc24M,