Commit 3907c492 authored by John Clements's avatar John Clements Committed by Alex Deucher
Browse files

drm/amdgpu: Add driver infrastructure for MCA RAS 



Add MCA specific IP blocks targetting RAS features

Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarJohn Clements <john.clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3341d30d

drivers/gpu/drm/amd/amdgpu/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \

	amdgpu_fw_attestation.o amdgpu_securedisplay.o amdgpu_hdp.o \

	amdgpu_eeprom.o

	amdgpu_eeprom.o amdgpu_mca.o



amdgpu-$(CONFIG_PROC_FS) += amdgpu_fdinfo.o
@@ -189,6 +189,10 @@ amdgpu-y += \ 
amdgpu-y += \

	amdgpu_reset.o



# add MCA block

amdgpu-y += \

	mca_v3_0.o



# add amdkfd interfaces

amdgpu-y += amdgpu_amdkfd.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+4 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ 
#include "amdgpu_df.h"

#include "amdgpu_smuio.h"

#include "amdgpu_fdinfo.h"

#include "amdgpu_mca.h"



#define MAX_GPU_INSTANCE		16
@@ -1009,6 +1010,9 @@ struct amdgpu_device { 
	/* df */

	struct amdgpu_df                df;



	/* MCA */

	struct amdgpu_mca               mca;



	struct amdgpu_ip_block          ip_blocks[AMDGPU_MAX_IP_NUM];

	uint32_t		        harvest_ip_mask;

	int				num_ip_blocks;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+21 −0
Original line number Diff line number Diff line
@@ -471,6 +471,27 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev) 
			return r;

	}



	if (adev->mca.mp0.ras_funcs &&

	    adev->mca.mp0.ras_funcs->ras_late_init) {

		r = adev->mca.mp0.ras_funcs->ras_late_init(adev);

		if (r)

			return r;

	}



	if (adev->mca.mp1.ras_funcs &&

	    adev->mca.mp1.ras_funcs->ras_late_init) {

		r = adev->mca.mp1.ras_funcs->ras_late_init(adev);

		if (r)

			return r;

	}



	if (adev->mca.mpio.ras_funcs &&

	    adev->mca.mpio.ras_funcs->ras_late_init) {

		r = adev->mca.mpio.ras_funcs->ras_late_init(adev);

		if (r)

			return r;

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c

0 → 100644
+117 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu_ras.h"

#include "amdgpu.h"

#include "amdgpu_mca.h"



#include "umc/umc_6_7_0_offset.h"

#include "umc/umc_6_7_0_sh_mask.h"



void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,

					      uint64_t mc_status_addr,

					      unsigned long *error_count)

{

	uint64_t mc_status = RREG64_PCIE(mc_status_addr * 4);



	if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)

		*error_count += 1;

}



void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,

						uint64_t mc_status_addr,

						unsigned long *error_count)

{

	uint64_t mc_status = RREG64_PCIE(mc_status_addr * 4);



	if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&

	    (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||

	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||

	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||

	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||

	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))

		*error_count += 1;

}



void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,

				  uint64_t mc_status_addr)

{

	WREG64_PCIE(mc_status_addr * 4, 0x0ULL);

}



void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,

				      uint64_t mc_status_addr,

				      void *ras_error_status)

{

	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;



	amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count));

	amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count));



	amdgpu_mca_reset_error_count(adev, mc_status_addr);

}



int amdgpu_mca_ras_late_init(struct amdgpu_device *adev,

			     struct amdgpu_mca_ras *mca_dev)

{

	int r;

	struct ras_ih_if ih_info = {

		.cb = NULL,

	};

	struct ras_fs_if fs_info = {

		.sysfs_name = mca_dev->ras_funcs->sysfs_name,

	};



	if (!mca_dev->ras_if) {

		mca_dev->ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);

		if (!mca_dev->ras_if)

			return -ENOMEM;

		mca_dev->ras_if->block = mca_dev->ras_funcs->ras_block;

		mca_dev->ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		mca_dev->ras_if->sub_block_index = 0;

	}

	ih_info.head = fs_info.head = *mca_dev->ras_if;

	r = amdgpu_ras_late_init(adev, mca_dev->ras_if,

				 &fs_info, &ih_info);

	if (r || !amdgpu_ras_is_supported(adev, mca_dev->ras_if->block)) {

		kfree(mca_dev->ras_if);

		mca_dev->ras_if = NULL;

	}



	return r;

}



void amdgpu_mca_ras_fini(struct amdgpu_device *adev,

			 struct amdgpu_mca_ras *mca_dev)

{

	struct ras_ih_if ih_info = {

		.cb = NULL,

	};



	if (!mca_dev->ras_if)

		return;



	amdgpu_ras_late_fini(adev, mca_dev->ras_if, &ih_info);

	kfree(mca_dev->ras_if);

	mca_dev->ras_if = NULL;

}
 
 No newline at end of file

drivers/gpu/drm/amd/amdgpu/amdgpu_mca.h

0 → 100644
+72 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2021  Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included

 * in all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN

 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN

 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef __AMDGPU_MCA_H__

#define __AMDGPU_MCA_H__



struct amdgpu_mca_ras_funcs {

	int (*ras_late_init)(struct amdgpu_device *adev);

	void (*ras_fini)(struct amdgpu_device *adev);

	void (*query_ras_error_count)(struct amdgpu_device *adev,

				      void *ras_error_status);

	void (*query_ras_error_address)(struct amdgpu_device *adev,

					void *ras_error_status);

	uint32_t ras_block;

	const char* sysfs_name;

};



struct amdgpu_mca_ras {

	struct ras_common_if *ras_if;

	const struct amdgpu_mca_ras_funcs *ras_funcs;

};



struct amdgpu_mca_funcs {

	void (*init)(struct amdgpu_device *adev);

};



struct amdgpu_mca {

	const struct amdgpu_mca_funcs *funcs;

	struct amdgpu_mca_ras mp0;

	struct amdgpu_mca_ras mp1;

	struct amdgpu_mca_ras mpio;

};



void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,

					      uint64_t mc_status_addr,

					      unsigned long *error_count);



void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,

						uint64_t mc_status_addr,

						unsigned long *error_count);



void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,

				  uint64_t mc_status_addr);



void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,

				      uint64_t mc_status_addr,

				      void *ras_error_status);



int amdgpu_mca_ras_late_init(struct amdgpu_device *adev,

			     struct amdgpu_mca_ras *mca_dev);



void amdgpu_mca_ras_fini(struct amdgpu_device *adev,

			 struct amdgpu_mca_ras *mca_dev);



#endif