Commit 38f88732 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-msm-next-2023-08-20' of https://gitlab.freedesktop.org/drm/msm into drm-next 



Updates for v6.6, which includes a backmerge of msm-fixes to avoid conficts.

Core:
- SM6125 MDSS support

DPU:
- SM6125 DPU support
- Added subblocks to display snapshot
- Use UBWC data from MDSS driver rather than duplicating it
- dpu_core_perf cleanup

DSI:
- Enabled burst mode to fix CMD mode panels
- Runtime PM support
- refgen regulator support

DSI PHY:
- SM6125 support in 14nm DSI PHY driver

GPU:
- Rework GPU identification to prepare for a7xx, and other a7xx prep
- Cleanups and fixes
- Disallow legacy relocs on a6xx and newer
- a690: switch to using a660_gmu.bin fw as this is what we have in
  linux-firmware and we see no evidence that it should be different
  from other a660 family (a6xx subgen 4) devices
- Submit overhead opts, 1.6x faster for NO_IMPLICIT_SYNC commits with
  100 BOs to 2.5x faster for 1000 BOs

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGv_01g-edjdfKLWWcb-rO5aSyLsv5FpbKrTkXVL9+ngTQ@mail.gmail.com
parents fdebffeb 34b149ec

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml

+22 −2
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ properties: 
      - description: Link clock from DP PHY

      - description: VCO DIV clock from DP PHY

      - description: AHB config clock from GCC

      - description: GPLL0 div source from GCC



  clock-names:

    items:
@@ -39,6 +40,7 @@ properties: 
      - const: dp_phy_pll_link_clk

      - const: dp_phy_pll_vco_div_clk

      - const: cfg_ahb_clk

      - const: gcc_disp_gpll0_div_clk_src



  '#clock-cells':

    const: 1
@@ -46,6 +48,16 @@ properties: 
  '#power-domain-cells':

    const: 1



  power-domains:

    description:

      A phandle and PM domain specifier for the CX power domain.

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing the power domain's performance point.

    maxItems: 1



  reg:

    maxItems: 1
@@ -63,23 +75,31 @@ examples: 
  - |

    #include <dt-bindings/clock/qcom,rpmcc.h>

    #include <dt-bindings/clock/qcom,gcc-sm6125.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    clock-controller@5f00000 {

      compatible = "qcom,sm6125-dispcc";

      reg = <0x5f00000 0x20000>;



      clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,

               <&dsi0_phy 0>,

               <&dsi0_phy 1>,

               <&dsi1_phy 1>,

               <&dp_phy 0>,

               <&dp_phy 1>,

               <&gcc GCC_DISP_AHB_CLK>;

               <&gcc GCC_DISP_AHB_CLK>,

               <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;

      clock-names = "bi_tcxo",

                    "dsi0_phy_pll_out_byteclk",

                    "dsi0_phy_pll_out_dsiclk",

                    "dsi1_phy_pll_out_dsiclk",

                    "dp_phy_pll_link_clk",

                    "dp_phy_pll_vco_div_clk",

                    "cfg_ahb_clk";

                    "cfg_ahb_clk",

                    "gcc_disp_gpll0_div_clk_src";



      required-opps = <&rpmhpd_opp_ret>;

      power-domains = <&rpmpd SM6125_VDDCX>;



      #clock-cells = <1>;

      #power-domain-cells = <1>;

    };

Documentation/devicetree/bindings/display/msm/dp-controller.yaml

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties: 
          - qcom,sm8350-dp

      - items:

          - enum:

              - qcom,sm8250-dp

              - qcom,sm8450-dp

              - qcom,sm8550-dp

          - const: qcom,sm8350-dp

Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

+6 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties: 
              - qcom,sdm660-dsi-ctrl

              - qcom,sdm845-dsi-ctrl

              - qcom,sm6115-dsi-ctrl

              - qcom,sm6125-dsi-ctrl

              - qcom,sm6350-dsi-ctrl

              - qcom,sm6375-dsi-ctrl

              - qcom,sm8150-dsi-ctrl
@@ -166,6 +167,10 @@ properties: 
    description:

      Phandle to vdd regulator device node



  refgen-supply:

    description:

      Phandle to REFGEN regulator device node



  vcca-supply:

    description:

      Phandle to vdd regulator device node
@@ -301,6 +306,7 @@ allOf: 
          contains:

            enum:

              - qcom,msm8998-dsi-ctrl

              - qcom,sm6125-dsi-ctrl

              - qcom,sm6350-dsi-ctrl

    then:

      properties:

Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml

+11 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ properties: 
      - qcom,dsi-phy-14nm-2290

      - qcom,dsi-phy-14nm-660

      - qcom,dsi-phy-14nm-8953

      - qcom,sm6125-dsi-phy-14nm



  reg:

    items:
@@ -35,6 +36,16 @@ properties: 
  vcca-supply:

    description: Phandle to vcca regulator device node.



  power-domains:

    description:

      A phandle and PM domain specifier for an optional power domain.

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing the power domain's performance point.

    maxItems: 1



required:

  - compatible

  - reg

Documentation/devicetree/bindings/display/msm/gpu.yaml

+6 −0
Original line number Diff line number Diff line
@@ -13,6 +13,12 @@ maintainers: 
properties:

  compatible:

    oneOf:

      - description: |

          The driver is parsing the compat string for Adreno to

          figure out the chip-id.

        items:

          - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$'

          - const: qcom,adreno

      - description: |

          The driver is parsing the compat string for Adreno to

          figure out the gpu-id and patch level.