Commit 38f46186 authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE 



EDP_Y_COORDINATE_ENABLE became a reserved register in display 13.
EDP_Y_COORDINATE_VALID have the same fate as EDP_Y_COORDINATE_ENABLE
but as we don't need it, removing the macro definition of it.

BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Reviewed-by: default avatarGwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210421220224.200729-2-jose.souza@intel.com
parent dc09b309

drivers/gpu/drm/i915/display/intel_psr.c

+1 −1
Original line number Diff line number Diff line
@@ -524,7 +524,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) 
	val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT;



	val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;

	if (DISPLAY_VER(dev_priv) >= 10)

	if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12)

		val |= EDP_Y_COORDINATE_ENABLE;



	val |= EDP_PSR2_FRAME_BEFORE_SU(intel_dp->psr.sink_sync_latency + 1);

drivers/gpu/drm/i915/i915_reg.h

+1 −2
Original line number Diff line number Diff line
@@ -4563,8 +4563,7 @@ enum { 
#define   EDP_SU_TRACK_ENABLE			(1 << 30)

#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_2	(0 << 28)

#define   TGL_EDP_PSR2_BLOCK_COUNT_NUM_3	(1 << 28)

#define   EDP_Y_COORDINATE_VALID		(1 << 26) /* GLK and CNL+ */

#define   EDP_Y_COORDINATE_ENABLE		(1 << 25) /* GLK and CNL+ */

#define   EDP_Y_COORDINATE_ENABLE		REG_BIT(25) /* display 10, 11 and 12 */

#define   EDP_MAX_SU_DISABLE_TIME(t)		((t) << 20)

#define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)

#define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	8