Commit 38624d2c authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2022-12-15' of... 

Merge tag 'drm-intel-next-fixes-2022-12-15' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- Documentation fixe (Matt, Miaoqian)
- OA-perf related fix (Umesh)
- VLV/CHV HDMI/DP audio fix (Ville)
- Display DDI/Transcoder fix (Khaled)
- Migrate fixes (Chris, Matt)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/Y5uFYOJ/1jgf2eSE@intel.com
parents 5504eb16 ad0fca2d

drivers/gpu/drm/i915/display/g4x_dp.c

+2 −2
Original line number Diff line number Diff line
@@ -673,8 +673,6 @@ static void intel_enable_dp(struct intel_atomic_state *state, 
	intel_dp_pcon_dsc_configure(intel_dp, pipe_config);

	intel_dp_start_link_train(intel_dp, pipe_config);

	intel_dp_stop_link_train(intel_dp, pipe_config);



	intel_audio_codec_enable(encoder, pipe_config, conn_state);

}



static void g4x_enable_dp(struct intel_atomic_state *state,
@@ -683,6 +681,7 @@ static void g4x_enable_dp(struct intel_atomic_state *state, 
			  const struct drm_connector_state *conn_state)

{

	intel_enable_dp(state, encoder, pipe_config, conn_state);

	intel_audio_codec_enable(encoder, pipe_config, conn_state);

	intel_edp_backlight_on(pipe_config, conn_state);

}
@@ -691,6 +690,7 @@ static void vlv_enable_dp(struct intel_atomic_state *state, 
			  const struct intel_crtc_state *pipe_config,

			  const struct drm_connector_state *conn_state)

{

	intel_audio_codec_enable(encoder, pipe_config, conn_state);

	intel_edp_backlight_on(pipe_config, conn_state);

}

drivers/gpu/drm/i915/display/g4x_hdmi.c

+19 −6
Original line number Diff line number Diff line
@@ -157,10 +157,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, 
			     &pipe_config->infoframes.hdmi);

}



static void g4x_enable_hdmi(struct intel_atomic_state *state,

			    struct intel_encoder *encoder,

			    const struct intel_crtc_state *pipe_config,

			    const struct drm_connector_state *conn_state)

static void g4x_hdmi_enable_port(struct intel_encoder *encoder,

				 const struct intel_crtc_state *pipe_config)

{

	struct drm_device *dev = encoder->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -175,6 +173,16 @@ static void g4x_enable_hdmi(struct intel_atomic_state *state, 


	intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);

	intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);

}



static void g4x_enable_hdmi(struct intel_atomic_state *state,

			    struct intel_encoder *encoder,

			    const struct intel_crtc_state *pipe_config,

			    const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	g4x_hdmi_enable_port(encoder, pipe_config);



	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&

		    !pipe_config->has_hdmi_sink);
@@ -294,6 +302,11 @@ static void vlv_enable_hdmi(struct intel_atomic_state *state, 
			    const struct intel_crtc_state *pipe_config,

			    const struct drm_connector_state *conn_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	drm_WARN_ON(&dev_priv->drm, pipe_config->has_audio &&

		    !pipe_config->has_hdmi_sink);

	intel_audio_codec_enable(encoder, pipe_config, conn_state);

}



static void intel_disable_hdmi(struct intel_atomic_state *state,
@@ -415,7 +428,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state, 
			      pipe_config->has_infoframe,

			      pipe_config, conn_state);



	g4x_enable_hdmi(state, encoder, pipe_config, conn_state);

	g4x_hdmi_enable_port(encoder, pipe_config);



	vlv_wait_port_ready(dev_priv, dig_port, 0x0);

}
@@ -492,7 +505,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state, 
			      pipe_config->has_infoframe,

			      pipe_config, conn_state);



	g4x_enable_hdmi(state, encoder, pipe_config, conn_state);

	g4x_hdmi_enable_port(encoder, pipe_config);



	vlv_wait_port_ready(dev_priv, dig_port, 0x0);

drivers/gpu/drm/i915/display/intel_dp.c

+0 −59
Original line number Diff line number Diff line
@@ -3679,61 +3679,6 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
	}

}



static void

intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,

				  const struct intel_crtc_state *crtc_state)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);

	enum pipe pipe = crtc->pipe;

	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;



	trans_ddi_func_ctl_value = intel_de_read(dev_priv,

						 TRANS_DDI_FUNC_CTL(pipe));

	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));

	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));



	trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |

				      TGL_TRANS_DDI_PORT_MASK);

	trans_conf_value &= ~PIPECONF_ENABLE;

	dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;



	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);

	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),

		       trans_ddi_func_ctl_value);

	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);

}



static void

intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,

				 const struct intel_crtc_state *crtc_state)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_device *dev = dig_port->base.base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	enum port port = dig_port->base.port;

	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);

	enum pipe pipe = crtc->pipe;

	u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;



	trans_ddi_func_ctl_value = intel_de_read(dev_priv,

						 TRANS_DDI_FUNC_CTL(pipe));

	trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));

	dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));



	trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |

				    TGL_TRANS_DDI_SELECT_PORT(port);

	trans_conf_value |= PIPECONF_ENABLE;

	dp_tp_ctl_value |= DP_TP_CTL_ENABLE;



	intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);

	intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);

	intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),

		       trans_ddi_func_ctl_value);

}



static void intel_dp_process_phy_request(struct intel_dp *intel_dp,

					 const struct intel_crtc_state *crtc_state)

{
@@ -3752,14 +3697,10 @@ static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 
	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,

				  link_status);



	intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);



	intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX);



	intel_dp_phy_pattern_update(intel_dp, crtc_state);



	intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);



	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,

			  intel_dp->train_set, crtc_state->lane_count);

drivers/gpu/drm/i915/gem/i915_gem_object.c

+3 −0
Original line number Diff line number Diff line
@@ -785,6 +785,9 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) 
	if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))

		return false;



	if (obj->flags & I915_BO_ALLOC_CCS_AUX)

		return true;



	for (i = 0; i < obj->mm.n_placements; i++) {

		/* Compression is not allowed for the objects with smem placement */

		if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)

drivers/gpu/drm/i915/gem/i915_gem_object_types.h

+6 −4
Original line number Diff line number Diff line
@@ -327,16 +327,18 @@ struct drm_i915_gem_object { 
 * dealing with userspace objects the CPU fault handler is free to ignore this.

 */

#define I915_BO_ALLOC_GPU_ONLY	  BIT(6)

#define I915_BO_ALLOC_CCS_AUX	  BIT(7)

#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \

			     I915_BO_ALLOC_VOLATILE | \

			     I915_BO_ALLOC_CPU_CLEAR | \

			     I915_BO_ALLOC_USER | \

			     I915_BO_ALLOC_PM_VOLATILE | \

			     I915_BO_ALLOC_PM_EARLY | \

			     I915_BO_ALLOC_GPU_ONLY)

#define I915_BO_READONLY          BIT(7)

#define I915_TILING_QUIRK_BIT     8 /* unknown swizzling; do not release! */

#define I915_BO_PROTECTED         BIT(9)

			     I915_BO_ALLOC_GPU_ONLY | \

			     I915_BO_ALLOC_CCS_AUX)

#define I915_BO_READONLY          BIT(8)

#define I915_TILING_QUIRK_BIT     9 /* unknown swizzling; do not release! */

#define I915_BO_PROTECTED         BIT(10)

	/**

	 * @mem_flags - Mutable placement-related flags

	 *