Commit 38254d19 authored by Thierry Reding's avatar Thierry Reding
Browse files

arm64: tegra: Order nodes alphabetically on Tegra210 



Device tree nodes are ordered by unit-address and alphabetically by name
if a node doesn't have a unit-address. The thermal sensor and timer
nodes were not sorted in the correct order, so do that now.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 40b4d824

arch/arm64/boot/dts/nvidia/tegra210.dtsi

+40 −40
Original line number Diff line number Diff line
@@ -1309,6 +1309,32 @@ 
		status = "disabled";

	};



	soctherm: thermal-sensor@700e2000 {

		compatible = "nvidia,tegra210-soctherm";

		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */

		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */

		reg-names = "soctherm-reg", "car-reg";

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "thermal", "edp";

		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,

			<&tegra_car TEGRA210_CLK_SOC_THERM>;

		clock-names = "tsensor", "soctherm";

		resets = <&tegra_car 78>;

		reset-names = "soctherm";

		#thermal-sensor-cells = <1>;



		throttle-cfgs {

			throttle_heavy: heavy {

				nvidia,priority = <100>;

				nvidia,cpu-throt-percent = <85>;

				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;



				#cooling-cells = <2>;

			};

		};

	};



	mipi: mipi@700e3000 {

		compatible = "nvidia,tegra210-mipi";

		reg = <0x0 0x700e3000 0x0 0x100>;
@@ -1694,46 +1720,6 @@ 
				      &{/cpus/cpu@2} &{/cpus/cpu@3}>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

		arm,no-tick-in-suspend;

	};



	soctherm: thermal-sensor@700e2000 {

		compatible = "nvidia,tegra210-soctherm";

		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */

		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */

		reg-names = "soctherm-reg", "car-reg";

		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "thermal", "edp";

		clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,

			<&tegra_car TEGRA210_CLK_SOC_THERM>;

		clock-names = "tsensor", "soctherm";

		resets = <&tegra_car 78>;

		reset-names = "soctherm";

		#thermal-sensor-cells = <1>;



		throttle-cfgs {

			throttle_heavy: heavy {

				nvidia,priority = <100>;

				nvidia,cpu-throt-percent = <85>;

				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;



				#cooling-cells = <2>;

			};

		};

	};



	thermal-zones {

		cpu {

			polling-delay-passive = <1000>;
@@ -1868,4 +1854,18 @@ 
			};

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10

				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		interrupt-parent = <&gic>;

		arm,no-tick-in-suspend;

	};

};