Commit 37cfd5e4 authored Aug 07, 2023 by Marco Felsch Committed by Abel Vesa Aug 14, 2023

clk: imx: pll14xx: align pdiv with reference manual



The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come
with a 6-bit pre-divider. Neither the reference manuals nor the
datasheets of these SoCs do mention any restrictions. Furthermore the
current code doesn't respect the restrictions from the comment too.

Therefore drop the restriction and align the max pre-divider (pdiv)
value to 63 to get more accurate frequencies.

Fixes: b09c68dc ("clk: imx: pll14xx: Support dynamic rates")
Cc: stable@vger.kernel.org
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Link: https://lore.kernel.org/r/20230807084744.1184791-1-m.felsch@pengutronix.de


Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

parent 4dd432d9

drivers/clk/imx/clk-pll14xx.c

+5 −6

Original line number	Diff line number	Diff line
		@@ -139,11 +139,10 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
		/*
		* Fractional PLL constrains:
		*
		* a) 6MHz <= prate <= 25MHz
		* b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz)
		* c) 64 <= m <= 1023
		* d) 0 <= s <= 6
		* e) -32768 <= k <= 32767
		* a) 1 <= p <= 63
		* b) 64 <= m <= 1023
		* c) 0 <= s <= 6
		* d) -32768 <= k <= 32767
		*
		* fvco = (m * 65536 + k) * prate / (p * 65536)
		*/
		@@ -186,7 +185,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat
		}

		/* Finally calculate best values */
		for (pdiv = 1; pdiv <= 7; pdiv++) {
		for (pdiv = 1; pdiv <= 63; pdiv++) {
		for (sdiv = 0; sdiv <= 6; sdiv++) {
		/* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
		mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);