Commit 37c72e4c authored by Vinod Koul's avatar Vinod Koul Committed by Stephen Boyd
Browse files

clk: qcom: gcc: Add missing UFS clocks for SM8150 



Add the missing ufs card and ufs phy clocks for SM8150. They were missed
in earlier addition of clock driver.

Fixes: 2a1d7eb8 ("clk: qcom: gcc: Add global clock controller driver for SM8150")
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent f73a4230

drivers/clk/qcom/gcc-sm8150.c

+84 −0
Original line number Diff line number Diff line
@@ -2873,6 +2873,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { 
	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x7501c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_card_rx_symbol_0_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x750ac,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_card_rx_symbol_1_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x75018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_card_tx_symbol_0_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_ufs_card_unipro_core_clk = {

	.halt_reg = 0x75058,

	.halt_check = BRANCH_HALT,
@@ -3053,6 +3092,45 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { 
	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x7701c,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_phy_rx_symbol_0_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x770ac,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_phy_rx_symbol_1_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



/* external clocks so add BRANCH_HALT_SKIP */

static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x77018,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_phy_tx_symbol_0_clk",

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_ufs_phy_unipro_core_clk = {

	.halt_reg = 0x77058,

	.halt_check = BRANCH_HALT,
@@ -3549,6 +3627,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { 
	[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,

	[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =

		&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,

	[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,

	[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,

	[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,

	[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,

	[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =

		&gcc_ufs_card_unipro_core_clk_src.clkr,
@@ -3566,6 +3647,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { 
	[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,

	[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,

	[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,

	[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,

	[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,

	[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,

	[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,

	[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =

		&gcc_ufs_phy_unipro_core_clk_src.clkr,