Unverified Commit 37a96b69 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!629 arm64: Add initial support for FEAT_WFxT 

Merge Pull Request from: @did-you-collect-the-wool-today 
 
The ARMv8.7 WFxT feature is a new take on the good old WFI/WFE
instructions as they behave the same way, only taking an extra timeout
parameter.

This small series aims at adding the minimal support for this feature,
enabling it for both the kernel and KVM. 
 
Link:https://gitee.com/openeuler/kernel/pulls/629

 

Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 824c7466 62291a4e

Documentation/arm64/cpu-feature-registers.rst

+2 −0
Original line number Diff line number Diff line
@@ -290,6 +290,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | RPRES                        | [7-4]   |    y    |

     +------------------------------+---------+---------+

     | WFXT                         | [3-0]   |    y    |

     +------------------------------+---------+---------+





Appendix I: Example

Documentation/arm64/elf_hwcaps.rst

+4 −0
Original line number Diff line number Diff line
@@ -257,6 +257,10 @@ HWCAP2_RPRES 


    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.



HWCAP2_WFXT



    Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/barrier.h

+4 −0
Original line number Diff line number Diff line
@@ -16,7 +16,11 @@ 


#define sev()		asm volatile("sev" : : : "memory")

#define wfe()		asm volatile("wfe" : : : "memory")

#define wfet(val)	asm volatile("msr s0_3_c1_c0_0, %0"	\

				     : : "r" (val) : "memory")

#define wfi()		asm volatile("wfi" : : : "memory")

#define wfit(val)	asm volatile("msr s0_3_c1_c0_1, %0"	\

				     : : "r" (val) : "memory")



#define isb()		asm volatile("isb" : : : "memory")

#define dmb(opt)	asm volatile("dmb " #opt : : : "memory")

arch/arm64/include/asm/cpucaps.h

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ 
#define ARM64_HAS_EPAN				65

#define ARM64_SPECTRE_BHB			66

#define ARM64_WORKAROUND_1742098	67

#define ARM64_HAS_WFXT				68



#define ARM64_NCAPS				80

arch/arm64/include/asm/esr.h

+6 −2
Original line number Diff line number Diff line
@@ -132,7 +132,10 @@ 
#define ESR_ELx_CV		(UL(1) << 24)

#define ESR_ELx_COND_SHIFT	(20)

#define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)

#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)

#define ESR_ELx_WFx_ISS_RN	(UL(0x1F) << 5)

#define ESR_ELx_WFx_ISS_RV	(UL(1) << 2)

#define ESR_ELx_WFx_ISS_TI	(UL(3) << 0)

#define ESR_ELx_WFx_ISS_WFxT	(UL(2) << 0)

#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)

#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)

#define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
@@ -145,7 +148,8 @@ 
#define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)



/* ESR value templates for specific events */

#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)

#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK |			\

				 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))

#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\

				 ESR_ELx_WFx_ISS_WFI)