Loading drivers/mtd/nand/xway_nand.c +14 −16 Original line number Diff line number Diff line Loading @@ -66,22 +66,23 @@ struct xway_nand_data { struct nand_chip chip; unsigned long csflags; void __iomem *nandaddr; }; static u8 xway_readb(struct mtd_info *mtd, int op) { struct nand_chip *chip = mtd_to_nand(mtd); void __iomem *nandaddr = chip->IO_ADDR_R; struct xway_nand_data *data = nand_get_controller_data(chip); return readb(nandaddr + op); return readb(data->nandaddr + op); } static void xway_writeb(struct mtd_info *mtd, int op, u8 value) { struct nand_chip *chip = mtd_to_nand(mtd); void __iomem *nandaddr = chip->IO_ADDR_W; struct xway_nand_data *data = nand_get_controller_data(chip); writeb(value, nandaddr + op); writeb(value, data->nandaddr + op); } static void xway_select_chip(struct mtd_info *mtd, int select) Loading Loading @@ -154,7 +155,6 @@ static int xway_nand_probe(struct platform_device *pdev) struct mtd_info *mtd; struct resource *res; int err; void __iomem *nandaddr; u32 cs; u32 cs_flag = 0; Loading @@ -165,16 +165,14 @@ static int xway_nand_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); nandaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(nandaddr)) return PTR_ERR(nandaddr); data->nandaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(data->nandaddr)) return PTR_ERR(data->nandaddr); nand_set_flash_node(&data->chip, pdev->dev.of_node); mtd = nand_to_mtd(&data->chip); mtd->dev.parent = &pdev->dev; data->chip.IO_ADDR_R = nandaddr; data->chip.IO_ADDR_W = nandaddr; data->chip.cmd_ctrl = xway_cmd_ctrl; data->chip.dev_ready = xway_dev_ready; data->chip.select_chip = xway_select_chip; Loading @@ -195,7 +193,7 @@ static int xway_nand_probe(struct platform_device *pdev) cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; /* setup the EBU to run in NAND mode on our base addr */ ltq_ebu_w32(CPHYSADDR(nandaddr) ltq_ebu_w32(CPHYSADDR(data->nandaddr) | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 Loading Loading
drivers/mtd/nand/xway_nand.c +14 −16 Original line number Diff line number Diff line Loading @@ -66,22 +66,23 @@ struct xway_nand_data { struct nand_chip chip; unsigned long csflags; void __iomem *nandaddr; }; static u8 xway_readb(struct mtd_info *mtd, int op) { struct nand_chip *chip = mtd_to_nand(mtd); void __iomem *nandaddr = chip->IO_ADDR_R; struct xway_nand_data *data = nand_get_controller_data(chip); return readb(nandaddr + op); return readb(data->nandaddr + op); } static void xway_writeb(struct mtd_info *mtd, int op, u8 value) { struct nand_chip *chip = mtd_to_nand(mtd); void __iomem *nandaddr = chip->IO_ADDR_W; struct xway_nand_data *data = nand_get_controller_data(chip); writeb(value, nandaddr + op); writeb(value, data->nandaddr + op); } static void xway_select_chip(struct mtd_info *mtd, int select) Loading Loading @@ -154,7 +155,6 @@ static int xway_nand_probe(struct platform_device *pdev) struct mtd_info *mtd; struct resource *res; int err; void __iomem *nandaddr; u32 cs; u32 cs_flag = 0; Loading @@ -165,16 +165,14 @@ static int xway_nand_probe(struct platform_device *pdev) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); nandaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(nandaddr)) return PTR_ERR(nandaddr); data->nandaddr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(data->nandaddr)) return PTR_ERR(data->nandaddr); nand_set_flash_node(&data->chip, pdev->dev.of_node); mtd = nand_to_mtd(&data->chip); mtd->dev.parent = &pdev->dev; data->chip.IO_ADDR_R = nandaddr; data->chip.IO_ADDR_W = nandaddr; data->chip.cmd_ctrl = xway_cmd_ctrl; data->chip.dev_ready = xway_dev_ready; data->chip.select_chip = xway_select_chip; Loading @@ -195,7 +193,7 @@ static int xway_nand_probe(struct platform_device *pdev) cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1; /* setup the EBU to run in NAND mode on our base addr */ ltq_ebu_w32(CPHYSADDR(nandaddr) ltq_ebu_w32(CPHYSADDR(data->nandaddr) | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1); ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 Loading