Commit 3795d7cc authored Sep 30, 2020 by Michael Walle Committed by Bartosz Golaszewski Sep 30, 2020

gpio: mpc8xxx: simplify ls1028a/ls1088a support



Some Layerscape/QoriQ SoCs have input buffers which needs to be enabled
first. This was done in two different ways in the driver. Unify it.

This was tested on a LS1028A SoC.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>

parent e0ab949f

drivers/gpio/gpio-mpc8xxx.c

+12 −33

Original line number	Diff line number	Diff line
		@@ -47,27 +47,6 @@ struct mpc8xxx_gpio_chip {
		unsigned int irqn;
		};

		/* The GPIO Input Buffer Enable register(GPIO_IBE) is used to
		* control the input enable of each individual GPIO port.
		* When an individual GPIO port’s direction is set to
		* input (GPIO_GPDIR[DRn=0]), the associated input enable must be
		* set (GPIOxGPIE[IEn]=1) to propagate the port value to the GPIO
		* Data Register.
		*/
		static int ls1028a_gpio_dir_in_init(struct gpio_chip *gc)
		{
		unsigned long flags;
		struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc);

		spin_lock_irqsave(&gc->bgpio_lock, flags);

		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);

		spin_unlock_irqrestore(&gc->bgpio_lock, flags);

		return 0;
		}

		/*
		* This hardware has a big endian bit assignment such that GPIO line 0 is
		* connected to bit 31, line 1 to bit 30 ... line 31 to bit 0.
		@@ -283,7 +262,6 @@ static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
		};

		struct mpc8xxx_gpio_devtype {
		int (gpio_dir_in_init)(struct gpio_chip chip);
		int (gpio_dir_out)(struct gpio_chip , unsigned int, int);
		int (gpio_get)(struct gpio_chip , unsigned int);
		int (irq_set_type)(struct irq_data , unsigned int);
		@@ -294,11 +272,6 @@ static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = {
		.irq_set_type = mpc512x_irq_set_type,
		};

		static const struct mpc8xxx_gpio_devtype ls1028a_gpio_devtype = {
		.gpio_dir_in_init = ls1028a_gpio_dir_in_init,
		.irq_set_type = mpc8xxx_irq_set_type,
		};

		static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = {
		.gpio_dir_out = mpc5125_gpio_dir_out,
		.irq_set_type = mpc512x_irq_set_type,
		@@ -319,8 +292,8 @@ static const struct of_device_id mpc8xxx_gpio_ids[] = {
		{ .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, },
		{ .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, },
		{ .compatible = "fsl,pq3-gpio", },
		{ .compatible = "fsl,ls1028a-gpio", .data = &ls1028a_gpio_devtype, },
		{ .compatible = "fsl,ls1088a-gpio", .data = &ls1028a_gpio_devtype, },
		{ .compatible = "fsl,ls1028a-gpio", },
		{ .compatible = "fsl,ls1088a-gpio", },
		{ .compatible = "fsl,qoriq-gpio", },
		{}
		};
		@@ -389,7 +362,16 @@ static int mpc8xxx_probe(struct platform_device *pdev)

		gc->to_irq = mpc8xxx_gpio_to_irq;

		if (of_device_is_compatible(np, "fsl,qoriq-gpio"))
		/*
		* The GPIO Input Buffer Enable register(GPIO_IBE) is used to control
		* the input enable of each individual GPIO port. When an individual
		* GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the
		* associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate
		* the port value to the GPIO Data Register.
		*/
		if (of_device_is_compatible(np, "fsl,qoriq-gpio") \|\|
		of_device_is_compatible(np, "fsl,ls1028a-gpio") \|\|
		of_device_is_compatible(np, "fsl,ls1088a-gpio"))
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff);

		ret = gpiochip_add_data(gc, mpc8xxx_gc);
		@@ -411,9 +393,6 @@ static int mpc8xxx_probe(struct platform_device *pdev)
		/* ack and mask all irqs */
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff);
		gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0);
		/* enable input buffer */
		if (devtype->gpio_dir_in_init)
		devtype->gpio_dir_in_init(gc);

		ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn,
		mpc8xxx_gpio_irq_cascade,