Commit 377d0221 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher
Browse files

drm/amdgpu: add RAS query support for VCN 4.0 



Initialize VCN RAS structure and add RAS status query function.

Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 214c7642

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c

+60 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "soc15_hw_ip.h"

#include "vcn_v2_0.h"

#include "mmsch_v4_0.h"

#include "vcn_v4_0.h"



#include "vcn/vcn_4_0_0_offset.h"

#include "vcn/vcn_4_0_0_sh_mask.h"
@@ -64,6 +65,7 @@ static int vcn_v4_0_set_powergating_state(void *handle, 
static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,

        int inst_idx, struct dpg_pause_state *new_state);

static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);

static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);



/**

 * vcn_v4_0_early_init - set function pointers
@@ -84,6 +86,7 @@ static int vcn_v4_0_early_init(void *handle) 


	vcn_v4_0_set_unified_ring_funcs(adev);

	vcn_v4_0_set_irq_funcs(adev);

	vcn_v4_0_set_ras_funcs(adev);



	return 0;

}
@@ -2001,3 +2004,60 @@ const struct amdgpu_ip_block_version vcn_v4_0_ip_block = 
	.rev = 0,

	.funcs = &vcn_v4_0_ip_funcs,

};



static uint32_t vcn_v4_0_query_poison_by_instance(struct amdgpu_device *adev,

			uint32_t instance, uint32_t sub_block)

{

	uint32_t poison_stat = 0, reg_value = 0;



	switch (sub_block) {

	case AMDGPU_VCN_V4_0_VCPU_VCODEC:

		reg_value = RREG32_SOC15(VCN, instance, regUVD_RAS_VCPU_VCODEC_STATUS);

		poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF);

		break;

	default:

		break;

	}



	if (poison_stat)

		dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",

			instance, sub_block);



	return poison_stat;

}



static bool vcn_v4_0_query_ras_poison_status(struct amdgpu_device *adev)

{

	uint32_t inst, sub;

	uint32_t poison_stat = 0;



	for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)

		for (sub = 0; sub < AMDGPU_VCN_V4_0_MAX_SUB_BLOCK; sub++)

			poison_stat +=

				vcn_v4_0_query_poison_by_instance(adev, inst, sub);



	return !!poison_stat;

}



const struct amdgpu_ras_block_hw_ops vcn_v4_0_ras_hw_ops = {

	.query_poison_status = vcn_v4_0_query_ras_poison_status,

};



static struct amdgpu_vcn_ras vcn_v4_0_ras = {

	.ras_block = {

		.hw_ops = &vcn_v4_0_ras_hw_ops,

	},

};



static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev)

{

	switch (adev->ip_versions[VCN_HWIP][0]) {

	case IP_VERSION(4, 0, 0):

		adev->vcn.ras = &vcn_v4_0_ras;

		break;

	default:

		break;

	}



	amdgpu_vcn_set_ras_funcs(adev);

}

drivers/gpu/drm/amd/amdgpu/vcn_v4_0.h

+6 −0
Original line number Diff line number Diff line
@@ -24,6 +24,12 @@ 
#ifndef __VCN_V4_0_H__

#define __VCN_V4_0_H__



enum amdgpu_vcn_v4_0_sub_block {

	AMDGPU_VCN_V4_0_VCPU_VCODEC = 0,



	AMDGPU_VCN_V4_0_MAX_SUB_BLOCK,

};



extern const struct amdgpu_ip_block_version vcn_v4_0_ip_block;



#endif /* __VCN_V4_0_H__ */