Commit 37644cac authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'gpio-updates-for-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Pull gpio updates from Bartosz Golaszewski:
 "Here are the updates for this merge window from the GPIO subsystem.

  We have more lines removed than added thanks to dropping of a driver
  for a platform that's no longer supported. Otherwise the changes are
  pretty straightforward: support for some new models, various
  improvements to existing drivers, some tweaks to the core library code
  and DT bindings updates.

  Summary:

   - remove gpio-vr41xx driver as the only platform using it got dropped
     too

   - add support for suspend/resume to gpio-davinci

   - improvements to the GPIO character device code

   - add support for disabling bias for in-kernel users (up until now
     only user-space could set it)

   - drop unused devm_gpio_free()

   - fix a refcount issue in gpiolib OF

   - use device match helpers where applicable

   - add support for a new model to gpio-rockchip

   - non-functional improvements in gpio-adp5588

   - improve and simplify teardown in gpio-twl4030 and gpio-ucb1400

   - modernize the gpio-74xx-mmio and gpio-adnp drivers

   - coding style improvements in gpio-xilinx, gpio-104-idi-48

   - support new model (pca9571) in gpio-pca9570

   - convert the DT bindings to YAML for gpio-mvebu and update the
     document

   - don't return error codes from remove() in gpio-brcmstb

   - add a library for the intel 8255 PPI interface and use it in
     drivers

   - reduce using magic numbers and improve code readability in several
     drivers

   - convert DT bindings to YAML for gpio-tpic2810

   - add new models to DT bindings for gpio-frl-imx

   - Kconfig improvements

   - other minor tweaks and improvements"

* tag 'gpio-updates-for-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (52 commits)
  dt-bindings: gpio: fsl-imx-gpio: Add i.MXRT compatibles
  gpio: 74xx-mmio: Use bits instead of plain numbers for flags
  gpio: xilinx: add missing blank line after declarations
  MAINTAINERS: Update Intel 8255 GPIO driver file list
  gpio: gpio-mm: Implement and utilize register structures
  gpio: 104-idi-48: Implement and utilize register structures
  gpio: 104-dio-48e: Implement and utilize register structures
  gpio: i8255: Introduce the Intel 8255 interface library module
  gpio: 104-idio-16: Implement and utilize register structures
  gpio: ws16c48: Implement and utilize register structures
  gpio: remove VR41XX related gpio driver
  dt-bindings: gpio: add pull-disable flag
  gpiolib: acpi: support bias pull disable
  gpiolib: of: support bias pull disable
  gpiolib: add support for bias pull disable
  gpio: 74xx-mmio: use bits.h macros for all masks
  gpio: 74xx-mmio: Check MMIO_74XX_DIR_IN flag in mmio_74xx_dir_in()
  gpio: 74xx-mmio: Make use of device properties
  gpiolib: cdev: compile out HTE unless CONFIG_HTE selected
  gpiolib: cdev: consolidate edge detector configuration flags
  ...
parents 5f084819 c4f0d16d
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@@ -72,7 +72,7 @@ mpp19 19 gpio, uart0(rxd), sdio(pw_off)
GPIO:
-----
For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.

Required properties:

+1 −1
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@@ -156,7 +156,7 @@ GPIO:
-----

For common binding part and usage, refer to
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml.

Required properties:

+2 −0
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@@ -37,6 +37,8 @@ properties:
              - fsl,imx8mp-gpio
              - fsl,imx8mq-gpio
              - fsl,imx8qxp-gpio
              - fsl,imxrt1050-gpio
              - fsl,imxrt1170-gpio
          - const: fsl,imx35-gpio

  reg:
+0 −93
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* Marvell EBU GPIO controller

Required properties:

- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
  "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".

    "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
    Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
    should be used for the Discovery MV78200.

    "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
    (MV78230, MV78260, MV78460).

    "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
    SoCs (either from AP or CP), see
    Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
    for specific details about the offset property.

- reg: Address and length of the register set for the device. Only one
  entry is expected, except for the "marvell,armadaxp-gpio" variant
  for which two entries are expected: one for the general registers,
  one for the per-cpu registers. Not used for marvell,armada-8k-gpio.

- interrupts: The list of interrupts that are used for all the pins
  managed by this GPIO bank. There can be more than one interrupt
  (example: 1 interrupt per 8 pins on Armada XP, which means 4
  interrupts per bank of 32 GPIOs).

- interrupt-controller: identifies the node as an interrupt controller

- #interrupt-cells: specifies the number of cells needed to encode an
  interrupt source. Should be two.
  The first cell is the GPIO number.
  The second cell is used to specify flags:
    bits[3:0] trigger type and level flags:
      1 = low-to-high edge triggered.
      2 = high-to-low edge triggered.
      4 = active high level-sensitive.
      8 = active low level-sensitive.

- gpio-controller: marks the device node as a gpio controller

- ngpios: number of GPIOs this controller has

- #gpio-cells: Should be two. The first cell is the pin number. The
  second cell is reserved for flags, unused at the moment.

Optional properties:

In order to use the GPIO lines in PWM mode, some additional optional
properties are required.

- compatible: Must contain "marvell,armada-370-gpio"

- reg: an additional register set is needed, for the GPIO Blink
  Counter on/off registers.

- reg-names: Must contain an entry "pwm" corresponding to the
  additional register range needed for PWM operation.

- #pwm-cells: Should be two. The first cell is the GPIO line number. The
  second cell is the period in nanoseconds.

- clocks: Must be a phandle to the clock for the GPIO controller.

Example:

		gpio0: gpio@d0018100 {
			compatible = "marvell,armadaxp-gpio";
			reg = <0xd0018100 0x40>,
			    <0xd0018800 0x30>;
			ngpios = <32>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <16>, <17>, <18>, <19>;
		};

		gpio1: gpio@18140 {
			compatible = "marvell,armada-370-gpio";
			reg = <0x18140 0x40>, <0x181c8 0x08>;
			reg-names = "gpio", "pwm";
			ngpios = <17>;
			gpio-controller;
			#gpio-cells = <2>;
			#pwm-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <87>, <88>, <89>;
			clocks = <&coreclk 0>;
		};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Marvell EBU GPIO controller

maintainers:
  - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  - Andrew Lunn <andrew@lunn.ch>

properties:
  compatible:
    oneOf:
      - enum:
          - marvell,armada-8k-gpio
          - marvell,orion-gpio

      - items:
          - enum:
              - marvell,mv78200-gpio
              - marvell,armada-370-gpio
          - const: marvell,orion-gpio

      - description: Deprecated binding
        items:
          - const: marvell,armadaxp-gpio
          - const: marvell,orion-gpio
        deprecated: true

  reg:
    description: |
      Address and length of the register set for the device. Not used for
      marvell,armada-8k-gpio.

      A second entry can be provided, for the PWM function using the GPIO Blink
      Counter on/off registers.
    minItems: 1
    maxItems: 2

  reg-names:
    items:
      - const: gpio
      - const: pwm
    minItems: 1

  offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the gpio registers (in bytes)

  interrupts:
    description: |
      The list of interrupts that are used for all the pins managed by this
      GPIO bank. There can be more than one interrupt (example: 1 interrupt
      per 8 pins on Armada XP, which means 4 interrupts per bank of 32
      GPIOs).
    minItems: 1
    maxItems: 4

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  gpio-controller: true

  ngpios:
    minimum: 1
    maximum: 32

  "#gpio-cells":
    const: 2

  marvell,pwm-offset:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: Offset in the register map for the pwm registers (in bytes)

  "#pwm-cells":
    description:
      The first cell is the GPIO line number. The second cell is the period
      in nanoseconds.
    const: 2

  clocks:
    description:
      Clock(s) used for PWM function.
    items:
      - description: Core clock
      - description: AXI bus clock
    minItems: 1

  clock-names:
    items:
      - const: core
      - const: axi
    minItems: 1

required:
  - compatible
  - gpio-controller
  - ngpios
  - "#gpio-cells"

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: marvell,armada-8k-gpio
    then:
      required:
        - offset
    else:
      required:
        - reg

unevaluatedProperties: true

examples:
  - |
    gpio@d0018100 {
      compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
      reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
      ngpios = <32>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <16>, <17>, <18>, <19>;
    };

  - |
    gpio@18140 {
      compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
      reg = <0x18140 0x40>, <0x181c8 0x08>;
      reg-names = "gpio", "pwm";
      ngpios = <17>;
      gpio-controller;
      #gpio-cells = <2>;
      #pwm-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
      interrupts = <87>, <88>, <89>;
      clocks = <&coreclk 0>;
    };
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