Commit 3733db1f authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas: Document RZ/G2UL SoC 



Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 53367bd2

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+4 −3
Original line number Diff line number Diff line
@@ -10,7 +10,7 @@ maintainers: 
  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.



  They provide the following functionalities:
@@ -23,6 +23,7 @@ description: | 
properties:

  compatible:

    enum:

      - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2}

      - renesas,r9a07g044-cpg # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg # RZ/V2L