Commit 3727ce67 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files

dt-bindings: clock: qcom,gcc-sdx65: drop core_bi_pll_test_se 



The test clock apparently it's not used by anyone upstream. Remove it.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-4-dmitry.baryshkov@linaro.org
parent 5fe4abe3

Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml

+2 −6
Original line number Diff line number Diff line
@@ -26,8 +26,6 @@ properties: 
      - description: Sleep clock source

      - description: PCIE Pipe clock source

      - description: USB3 phy wrapper pipe clock source

      - description: PLL test clock source (Optional clock)

    minItems: 5



  clock-names:

    items:
@@ -36,8 +34,6 @@ properties: 
      - const: sleep_clk

      - const: pcie_pipe_clk

      - const: usb3_phy_wrapper_gcc_usb30_pipe_clk

      - const: core_bi_pll_test_se # Optional clock

    minItems: 5



required:

  - compatible
@@ -56,9 +52,9 @@ examples: 
      compatible = "qcom,gcc-sdx65";

      reg = <0x100000 0x1f7400>;

      clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;

               <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";

                    "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;