Commit 372428db authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I
Browse files

phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources 



Certain platforms like TI J721E using Cadence Sierra Serdes
doesn't provide explicit phy_clk and reset (APB reset) control.
Make them optional here.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 56d34730

drivers/phy/cadence/phy-cadence-sierra.c

+2 −2
Original line number Diff line number Diff line
@@ -193,7 +193,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, sp);



	sp->clk = devm_clk_get(dev, "phy_clk");

	sp->clk = devm_clk_get_optional(dev, "phy_clk");

	if (IS_ERR(sp->clk)) {

		dev_err(dev, "failed to get clock phy_clk\n");

		return PTR_ERR(sp->clk);
@@ -205,7 +205,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev) 
		return PTR_ERR(sp->phy_rst);

	}



	sp->apb_rst = devm_reset_control_get(dev, "sierra_apb");

	sp->apb_rst = devm_reset_control_get_optional(dev, "sierra_apb");

	if (IS_ERR(sp->apb_rst)) {

		dev_err(dev, "failed to get apb reset\n");

		return PTR_ERR(sp->apb_rst);