Commit 37237b5b authored by Alexander Lobakin's avatar Alexander Lobakin Committed by David S. Miller
Browse files

qed: reformat several structures a bit 



Prior to adding new fields and bitfields, reformat the related
structures according to the Linux style (spaces to tabs,
lowercase hex, indentation etc.).

Signed-off-by: default avatarAlexander Lobakin <alobakin@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3c41486e

drivers/net/ethernet/qlogic/qed/qed_hsi.h

+130 −126
Original line number Diff line number Diff line
@@ -11537,7 +11537,7 @@ typedef u32 offsize_t; /* In DWORDS !!! */ 
/* PHY configuration */

struct eth_phy_cfg {

	u32					speed;

#define ETH_SPEED_AUTONEG	0

#define ETH_SPEED_AUTONEG			0x0

#define ETH_SPEED_SMARTLINQ			0x8



	u32					pause;
@@ -11547,23 +11547,24 @@ struct eth_phy_cfg { 
#define ETH_PAUSE_TX				0x4



	u32					adv_speed;



	u32					loopback_mode;

#define ETH_LOOPBACK_NONE		(0)

#define ETH_LOOPBACK_INT_PHY		(1)

#define ETH_LOOPBACK_EXT_PHY		(2)

#define ETH_LOOPBACK_EXT		(3)

#define ETH_LOOPBACK_MAC		(4)

#define ETH_LOOPBACK_NONE			0x0

#define ETH_LOOPBACK_INT_PHY			0x1

#define ETH_LOOPBACK_EXT_PHY			0x2

#define ETH_LOOPBACK_EXT			0x3

#define ETH_LOOPBACK_MAC			0x4



	u32					eee_cfg;

#define EEE_CFG_EEE_ENABLED			BIT(0)

#define EEE_CFG_TX_LPI				BIT(1)

#define EEE_CFG_ADV_SPEED_1G			BIT(2)

#define EEE_CFG_ADV_SPEED_10G			BIT(3)

#define EEE_TX_TIMER_USEC_MASK			(0xfffffff0)

#define EEE_TX_TIMER_USEC_MASK			0xfffffff0

#define EEE_TX_TIMER_USEC_OFFSET		4

#define EEE_TX_TIMER_USEC_BALANCED_TIME		(0xa00)

#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	(0x100)

#define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)

#define EEE_TX_TIMER_USEC_BALANCED_TIME		0xa00

#define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	0x100

#define EEE_TX_TIMER_USEC_LATENCY_TIME		0x6000



	u32 feature_config_flags;

#define ETH_EEE_MODE_ADV_LPI		(1 << 0)
@@ -11908,12 +11909,9 @@ struct public_port { 
#define LINK_STATUS_SPEED_AND_DUPLEX_50G		(6 << 1)

#define LINK_STATUS_SPEED_AND_DUPLEX_100G		(7 << 1)

#define LINK_STATUS_SPEED_AND_DUPLEX_25G		(8 << 1)



#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED		0x00000020



#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE		0x00000040

#define LINK_STATUS_PARALLEL_DETECTION_USED		0x00000080



#define LINK_STATUS_PFC_ENABLED				0x00000100

#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE	0x00000200

#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE	0x00000400
@@ -11923,13 +11921,11 @@ struct public_port { 
#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000

#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000

#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000



#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000

#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000c0000

#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)

#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1 << 18)

#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2 << 18)

#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3 << 18)



#define LINK_STATUS_SFP_TX_FAULT			0x00100000

#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000

#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
@@ -12631,23 +12627,23 @@ struct public_drv_mb { 
#define FW_MSG_CODE_MDUMP_INVALID_CMD		0x00030000



	u32						fw_mb_param;

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xffff0000

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT	16

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000ffff

#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT	0



	/* get pf rdma protocol command responce */

	/* Get PF RDMA protocol command response */

#define FW_MB_PARAM_GET_PF_RDMA_NONE			0x0

#define FW_MB_PARAM_GET_PF_RDMA_ROCE			0x1

#define FW_MB_PARAM_GET_PF_RDMA_IWARP			0x2

#define FW_MB_PARAM_GET_PF_RDMA_BOTH			0x3



/* get MFW feature support response */

	/* Get MFW feature support response */

#define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ		0x00000001

#define FW_MB_PARAM_FEATURE_SUPPORT_EEE			0x00000002

#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK		0x00010000



#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR	(1 << 0)

#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR		BIT(0)



#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK	0x00000001

#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT	0
@@ -12658,7 +12654,7 @@ struct public_drv_mb { 
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK		0x00000008

#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT	3



#define FW_MB_PARAM_PPFID_BITMAP_MASK	0xFF

#define FW_MB_PARAM_PPFID_BITMAP_MASK			0xff

#define FW_MB_PARAM_PPFID_BITMAP_SHIFT			0



	u32						drv_pulse_mb;
@@ -13048,24 +13044,27 @@ struct nvm_cfg1_path { 
};



struct nvm_cfg1_port {

	u32 reserved__m_relocated_to_option_123;

	u32 reserved__m_relocated_to_option_124;

	u32							rel_to_opt123;

	u32							rel_to_opt124;



	u32							generic_cont0;

#define NVM_CFG1_PORT_DCBX_MODE_MASK				0x000F0000

#define NVM_CFG1_PORT_DCBX_MODE_MASK				0x000f0000

#define NVM_CFG1_PORT_DCBX_MODE_OFFSET				16

#define NVM_CFG1_PORT_DCBX_MODE_DISABLED			0x0

#define NVM_CFG1_PORT_DCBX_MODE_IEEE				0x1

#define NVM_CFG1_PORT_DCBX_MODE_CEE				0x2

#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC				0x3

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK		0x00F00000

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK		0x00f00000

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET		20

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET	0x1

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE		0x2

#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI		0x4



	u32							pcie_cfg;

	u32							features;



	u32							speed_cap_mask;

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK		0x0000FFFF

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK		0x0000ffff

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET		0

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G		0x1

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G		0x2
@@ -13074,8 +13073,9 @@ struct nvm_cfg1_port { 
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G		0x10

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G		0x20

#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G		0x40



	u32							link_settings;

#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK			0x0000000F

#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK			0x0000000f

#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET			0

#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG			0x0

#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G				0x1
@@ -13091,12 +13091,13 @@ struct nvm_cfg1_port { 
#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG			0x1

#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX			0x2

#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX			0x4



	u32							phy_cfg;

	u32							mgmt_traffic;



	u32							ext_phy;

	/* EEE power saving mode */

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00FF0000

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00ff0000

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET		16

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED		0x0

#define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED		0x1
@@ -13110,14 +13111,16 @@ struct nvm_cfg1_port { 
	u32							led_port_settings;

	u32							transceiver_00;

	u32							device_ids;



	u32							board_cfg;

#define NVM_CFG1_PORT_PORT_TYPE_MASK                            0x000000FF

#define NVM_CFG1_PORT_PORT_TYPE_MASK				0x000000ff

#define NVM_CFG1_PORT_PORT_TYPE_OFFSET				0

#define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED			0x0

#define NVM_CFG1_PORT_PORT_TYPE_MODULE				0x1

#define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE			0x2

#define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY				0x3

#define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE			0x4



	u32							mnm_10g_cap;

	u32							mnm_10g_ctrl;

	u32							mnm_10g_misc;
@@ -13133,6 +13136,7 @@ struct nvm_cfg1_port { 
	u32							mnm_100g_cap;

	u32							mnm_100g_ctrl;

	u32							mnm_100g_misc;



	u32							reserved[116];

};

drivers/net/ethernet/qlogic/qed/qed_mcp.h

+42 −43
Original line number Diff line number Diff line
@@ -50,7 +50,6 @@ struct qed_mcp_link_capabilities { 


struct qed_mcp_link_state {

	bool					link_up;



	u32					min_pf_rate;



	/* Actual link speed in Mb/s */
@@ -60,13 +59,14 @@ struct qed_mcp_link_state { 
	 * according to PF max bandwidth configuration.

	 */

	u32					speed;

	bool    full_duplex;



	bool					full_duplex;

	bool					an;

	bool					an_complete;

	bool					parallel_detection;

	bool					pfc_enabled;



	u32					partner_adv_speed;

#define QED_LINK_PARTNER_SPEED_1G_HD		BIT(0)

#define QED_LINK_PARTNER_SPEED_1G_FD		BIT(1)

#define QED_LINK_PARTNER_SPEED_10G		BIT(2)
@@ -75,15 +75,14 @@ struct qed_mcp_link_state { 
#define QED_LINK_PARTNER_SPEED_40G		BIT(5)

#define QED_LINK_PARTNER_SPEED_50G		BIT(6)

#define QED_LINK_PARTNER_SPEED_100G		BIT(7)

	u32     partner_adv_speed;



	bool					partner_tx_flow_ctrl_en;

	bool					partner_rx_flow_ctrl_en;



#define QED_LINK_PARTNER_SYMMETRIC_PAUSE (1)

#define QED_LINK_PARTNER_ASYMMETRIC_PAUSE (2)

#define QED_LINK_PARTNER_BOTH_PAUSE (3)

	u8					partner_adv_pause;

#define QED_LINK_PARTNER_SYMMETRIC_PAUSE	0x1

#define QED_LINK_PARTNER_ASYMMETRIC_PAUSE	0x2

#define QED_LINK_PARTNER_BOTH_PAUSE		0x3



	bool					sfp_tx_fault;

	bool					eee_active;

include/linux/qed/qed_if.h

+33 −31
Original line number Diff line number Diff line
@@ -664,28 +664,30 @@ enum qed_protocol { 
struct qed_link_params {

	bool					link_up;



	u32					override_flags;

#define QED_LINK_OVERRIDE_SPEED_AUTONEG		BIT(0)

#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS	BIT(1)

#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED	BIT(2)

#define QED_LINK_OVERRIDE_PAUSE_CONFIG		BIT(3)

#define QED_LINK_OVERRIDE_LOOPBACK_MODE		BIT(4)

#define QED_LINK_OVERRIDE_EEE_CONFIG		BIT(5)

	u32	override_flags;

	bool	autoneg;



	bool					autoneg;

	__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);



	u32					forced_speed;



	u32					pause_config;

#define QED_LINK_PAUSE_AUTONEG_ENABLE		BIT(0)

#define QED_LINK_PAUSE_RX_ENABLE		BIT(1)

#define QED_LINK_PAUSE_TX_ENABLE		BIT(2)

	u32	pause_config;



	u32					loopback_mode;

#define QED_LINK_LOOPBACK_NONE			BIT(0)

#define QED_LINK_LOOPBACK_INT_PHY		BIT(1)

#define QED_LINK_LOOPBACK_EXT_PHY		BIT(2)

#define QED_LINK_LOOPBACK_EXT			BIT(3)

#define QED_LINK_LOOPBACK_MAC			BIT(4)

	u32	loopback_mode;



	struct qed_link_eee_params		eee;

};