Commit 3721d4fb authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/reg: stop using implicit dev_priv in DSPCLK_GATE_D 



Remove the implicit dev_priv usage in DSPCLK_GATE_D register, and pass
it as parameter.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/41ca83573ca2d94bea568058f8cb8c35e814f8b1.1661855191.git.jani.nikula@intel.com
parent 6d737d9b

drivers/gpu/drm/i915/display/intel_display_power_well.c

+2 −2
Original line number Diff line number Diff line
@@ -1157,10 +1157,10 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 
	 * (and never recovering) in this case. intel_dsi_post_disable() will

	 * clear it when we turn off the display.

	 */

	val = intel_de_read(dev_priv, DSPCLK_GATE_D);

	val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));

	val &= DPOUNIT_CLOCK_GATE_DISABLE;

	val |= VRHUNIT_CLOCK_GATE_DISABLE;

	intel_de_write(dev_priv, DSPCLK_GATE_D, val);

	intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);



	/*

	 * Disable trickle feed and enable pnd deadline calculation

drivers/gpu/drm/i915/display/intel_gmbus.c

+2 −2
Original line number Diff line number Diff line
@@ -183,12 +183,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 
	u32 val;



	/* When using bit bashing for I2C, this bit needs to be set to 1 */

	val = intel_de_read(dev_priv, DSPCLK_GATE_D);

	val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));

	if (!enable)

		val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;

	else

		val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;

	intel_de_write(dev_priv, DSPCLK_GATE_D, val);

	intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);

}



static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,

drivers/gpu/drm/i915/display/intel_overlay.c

+2 −2
Original line number Diff line number Diff line
@@ -211,9 +211,9 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 


	/* WA_OVERLAY_CLKGATE:alm */

	if (enable)

		intel_de_write(dev_priv, DSPCLK_GATE_D, 0);

		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), 0);

	else

		intel_de_write(dev_priv, DSPCLK_GATE_D,

		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv),

			       OVRUNIT_CLOCK_GATE_DISABLE);



	/* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */

drivers/gpu/drm/i915/display/vlv_dsi.c

+4 −4
Original line number Diff line number Diff line
@@ -822,9 +822,9 @@ static void intel_dsi_pre_enable(struct intel_atomic_state *state, 
		u32 val;



		/* Disable DPOunit clock gating, can stall pipe */

		val = intel_de_read(dev_priv, DSPCLK_GATE_D);

		val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));

		val |= DPOUNIT_CLOCK_GATE_DISABLE;

		intel_de_write(dev_priv, DSPCLK_GATE_D, val);

		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);

	}



	if (!IS_GEMINILAKE(dev_priv))
@@ -998,9 +998,9 @@ static void intel_dsi_post_disable(struct intel_atomic_state *state, 


		vlv_dsi_pll_disable(encoder);



		val = intel_de_read(dev_priv, DSPCLK_GATE_D);

		val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv));

		val &= ~DPOUNIT_CLOCK_GATE_DISABLE;

		intel_de_write(dev_priv, DSPCLK_GATE_D, val);

		intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv), val);

	}



	/* Assert reset */

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -1637,7 +1637,7 @@ 
#define  DSTATE_PLL_D3_OFF			(1 << 3)

#define  DSTATE_GFX_CLOCK_GATING		(1 << 1)

#define  DSTATE_DOT_CLOCK_GATING		(1 << 0)

#define DSPCLK_GATE_D	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x6200)

#define DSPCLK_GATE_D(__i915)		_MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)

# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */

# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */

# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */