Commit 370bf628 authored by Rex-BC Chen's avatar Rex-BC Chen Committed by Stephen Boyd
Browse files

clk: mediatek: reset: Merge and revise reset register function 



There are two versions for clock reset register control for MediaTek
SoCs. The old hardware is one bit per reset control, and does not
have separate registers for bit set, clear and read-back operations.
This matches the scheme supported by the simple reset driver.

However, because we need to use different data structure from
reset_simple_data, we can not use the operation of simple reset
driver.
For this reason, we keep the original functions and name this version
as "MTK_RST_SIMPLE".

In this patch:
- Add a version enumeration to separate different reset hardware.
- Merge the reset register function of simple and set_clr into one
  function "mtk_register_reset_controller".
- Rename input variable "num_regs" to "rst_bank_nr" to avoid
  confusion. This variable is used to define the quantity of reset bank.
- Document mtk_reset_version and mtk_register_reset_controller.

Signed-off-by: default avatarRex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: default avatarNícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-6-rex-bc.chen@mediatek.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 11425757

drivers/clk/mediatek/clk-mt2701-eth.c

+1 −1
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) 
			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	mtk_register_reset_controller(node, 1, 0x34);

	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);



	return r;

}

drivers/clk/mediatek/clk-mt2701-g3d.c

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) 
			"could not register clock provider: %s: %d\n",

			pdev->name, r);



	mtk_register_reset_controller(node, 1, 0xc);

	mtk_register_reset_controller(node, 1, 0xc, MTK_RST_SIMPLE);



	return r;

}

drivers/clk/mediatek/clk-mt2701-hif.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) 
		return r;

	}



	mtk_register_reset_controller(node, 1, 0x34);

	mtk_register_reset_controller(node, 1, 0x34, MTK_RST_SIMPLE);



	return 0;

}

drivers/clk/mediatek/clk-mt2701.c

+2 −2
Original line number Diff line number Diff line
@@ -787,7 +787,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) 
	if (r)

		return r;



	mtk_register_reset_controller(node, 2, 0x30);

	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);



	return 0;

}
@@ -910,7 +910,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) 
	if (r)

		return r;



	mtk_register_reset_controller(node, 2, 0x0);

	mtk_register_reset_controller(node, 2, 0x0, MTK_RST_SIMPLE);



	return 0;

}

drivers/clk/mediatek/clk-mt2712.c

+2 −2
Original line number Diff line number Diff line
@@ -1361,7 +1361,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) 
		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



	mtk_register_reset_controller(node, 2, 0x30);

	mtk_register_reset_controller(node, 2, 0x30, MTK_RST_SIMPLE);



	return r;

}
@@ -1383,7 +1383,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) 
		pr_err("%s(): could not register clock provider: %d\n",

			__func__, r);



	mtk_register_reset_controller(node, 2, 0);

	mtk_register_reset_controller(node, 2, 0, MTK_RST_SIMPLE);



	return r;

}