Commit 36de13fd authored by Yang Wang's avatar Yang Wang Committed by Alex Deucher
Browse files

drm/amdgpu: change the alignment size of TMR BO to 1M 



align TMR BO size TO tmr size is not necessary,
modify the size to 1M to avoid re-create BO fail
when serious VRAM fragmentation.

v2:
add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size

Signed-off-by: default avatarYang Wang <KevinYang.Wang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent df2c6e0c

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+1 −1
Original line number Diff line number Diff line
@@ -756,7 +756,7 @@ static int psp_tmr_init(struct psp_context *psp) 
	}



	pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;

	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),

	ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,

				      AMDGPU_GEM_DOMAIN_VRAM,

				      &psp->tmr_bo, &psp->tmr_mc_addr, pptr);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define PSP_CMD_BUFFER_SIZE	0x1000

#define PSP_1_MEG		0x100000

#define PSP_TMR_SIZE(adev)	((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)

#define PSP_TMR_ALIGNMENT	0x100000

#define PSP_FW_NAME_LEN		0x24



enum psp_shared_mem_size {