drm/i915: move dpll under display.dpll (36d225f3) · Commits · EulixOS / Software / Kernel

drivers/gpu/drm/i915/display/icl_dsi.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -642,13 +642,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
		u32 tmp;
		enum phy phy;

		mutex_lock(&dev_priv->dpll.lock);
		mutex_lock(&dev_priv->display.dpll.lock);
		tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
		for_each_dsi_phy(phy, intel_dsi->phys)
		tmp \|= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
		mutex_unlock(&dev_priv->dpll.lock);
		mutex_unlock(&dev_priv->display.dpll.lock);
		}

		static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
		@@ -658,13 +658,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
		u32 tmp;
		enum phy phy;

		mutex_lock(&dev_priv->dpll.lock);
		mutex_lock(&dev_priv->display.dpll.lock);
		tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
		for_each_dsi_phy(phy, intel_dsi->phys)
		tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);

		intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
		mutex_unlock(&dev_priv->dpll.lock);
		mutex_unlock(&dev_priv->display.dpll.lock);
		}

		static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
		@@ -694,7 +694,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
		enum phy phy;
		u32 val;

		mutex_lock(&dev_priv->dpll.lock);
		mutex_lock(&dev_priv->display.dpll.lock);

		val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
		for_each_dsi_phy(phy, intel_dsi->phys) {
		@@ -710,7 +710,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,

		intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);

		mutex_unlock(&dev_priv->dpll.lock);
		mutex_unlock(&dev_priv->display.dpll.lock);
		}

		static void

drivers/gpu/drm/i915/display/intel_ddi.c

+12 −12

Original line number	Diff line number	Diff line
		@@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
		static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
		u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
		{
		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);

		@@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
		*/
		intel_de_rmw(i915, reg, clk_off, 0);

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);
		}

		static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
		u32 clk_off)
		{
		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, reg, 0, clk_off);

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);
		}

		static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
		@@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
		intel_de_write(i915, DDI_CLK_SEL(port),
		icl_pll_to_ddi_clk_sel(encoder, crtc_state));

		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
		ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);
		}

		static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
		@@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
		enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
		enum port port = encoder->port;

		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
		0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);

		intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
		}
		@@ -1824,7 +1824,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
		if (drm_WARN_ON(&i915->drm, !pll))
		return;

		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, DPLL_CTRL2,
		DPLL_CTRL2_DDI_CLK_OFF(port) \|
		@@ -1832,7 +1832,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
		DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) \|
		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);
		}

		static void skl_ddi_disable_clock(struct intel_encoder *encoder)
		@@ -1840,12 +1840,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
		struct drm_i915_private *i915 = to_i915(encoder->base.dev);
		enum port port = encoder->port;

		mutex_lock(&i915->dpll.lock);
		mutex_lock(&i915->display.dpll.lock);

		intel_de_rmw(i915, DPLL_CTRL2,
		0, DPLL_CTRL2_DDI_CLK_OFF(port));

		mutex_unlock(&i915->dpll.lock);
		mutex_unlock(&i915->display.dpll.lock);
		}

		static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)

drivers/gpu/drm/i915/display/intel_display.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1488,7 +1488,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
		* Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
		* TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
		*/
		if (i915->dpll.mgr) {
		if (i915->display.dpll.mgr) {
		for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
		if (intel_crtc_needs_modeset(new_crtc_state))
		continue;
		@@ -5840,7 +5840,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,

		PIPE_CONF_CHECK_BOOL(double_wide);

		if (dev_priv->dpll.mgr) {
		if (dev_priv->display.dpll.mgr) {
		PIPE_CONF_CHECK_P(shared_dpll);

		PIPE_CONF_CHECK_X(dpll_hw_state.dpll);

drivers/gpu/drm/i915/display/intel_display_core.h

+21 −0

Original line number	Diff line number	Diff line
		@@ -12,6 +12,7 @@

		#include "intel_display.h"
		#include "intel_dmc.h"
		#include "intel_dpll_mgr.h"
		#include "intel_gmbus.h"

		struct drm_i915_private;
		@@ -23,6 +24,7 @@ struct intel_color_funcs;
		struct intel_crtc;
		struct intel_crtc_state;
		struct intel_dpll_funcs;
		struct intel_dpll_mgr;
		struct intel_fdi_funcs;
		struct intel_hotplug_funcs;
		struct intel_initial_plane_config;
		@@ -79,6 +81,24 @@ struct intel_audio {
		} lpe;
		};

		/*
		* dpll and cdclk state is protected by connection_mutex dpll.lock serializes
		* intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
		* dpll, because on some platforms plls share registers.
		*/
		struct intel_dpll {
		struct mutex lock;

		int num_shared_dpll;
		struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
		const struct intel_dpll_mgr *mgr;

		struct {
		int nssc;
		int ssc;
		} ref_clks;
		};

		struct intel_display {
		/* Display functions */
		struct {
		@@ -136,6 +156,7 @@ struct intel_display {
		/* Grouping using named structs. Keep sorted. */
		struct intel_audio audio;
		struct intel_dmc dmc;
		struct intel_dpll dpll;
		};

		#endif /* __INTEL_DISPLAY_CORE_H__ */

drivers/gpu/drm/i915/display/intel_display_debugfs.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -933,11 +933,11 @@ static int i915_shared_dplls_info(struct seq_file m, void unused)
		drm_modeset_lock_all(dev);

		seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
		dev_priv->dpll.ref_clks.nssc,
		dev_priv->dpll.ref_clks.ssc);
		dev_priv->display.dpll.ref_clks.nssc,
		dev_priv->display.dpll.ref_clks.ssc);

		for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
		for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
		struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];

		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
		pll->info->id);