Loading arch/powerpc/include/asm/asm-405.h 0 → 100644 +19 −0 Original line number Diff line number Diff line #ifndef _ASM_POWERPC_ASM_405_H #define _ASM_POWERPC_ASM_405_H #include <asm/asm-const.h> #ifdef __KERNEL__ #ifdef CONFIG_IBM405_ERR77 /* Erratum #77 on the 405 means we need a sync or dcbt before every * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this. */ #define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;) #define PPC405_ERR77_SYNC stringify_in_c(sync;) #else #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif #endif #endif /* _ASM_POWERPC_ASM_405_H */ arch/powerpc/include/asm/asm-compat.h +0 −13 Original line number Diff line number Diff line Loading @@ -70,17 +70,4 @@ #endif #ifdef __KERNEL__ #ifdef CONFIG_IBM405_ERR77 /* Erratum #77 on the 405 means we need a sync or dcbt before every * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this. */ #define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;) #define PPC405_ERR77_SYNC stringify_in_c(sync;) #else #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif #endif #endif /* _ASM_POWERPC_ASM_COMPAT_H */ arch/powerpc/include/asm/atomic.h +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ #include <linux/types.h> #include <asm/cmpxchg.h> #include <asm/barrier.h> #include <asm/asm-405.h> #define ATOMIC_INIT(i) { (i) } Loading arch/powerpc/include/asm/bitops.h +1 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,7 @@ #include <linux/compiler.h> #include <asm/asm-compat.h> #include <asm/synch.h> #include <asm/asm-405.h> /* PPC bit number conversion */ #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) Loading arch/powerpc/include/asm/book3s/32/pgtable.h +0 −2 Original line number Diff line number Diff line Loading @@ -164,7 +164,6 @@ static inline unsigned long pte_update(pte_t *p, 1: lwarx %0,0,%3\n\ andc %1,%0,%4\n\ or %1,%1,%5\n" PPC405_ERR77(0,%3) " stwcx. %1,0,%3\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) Loading @@ -186,7 +185,6 @@ static inline unsigned long long pte_update(pte_t *p, lwzx %0,0,%3\n\ andc %1,%L0,%5\n\ or %1,%1,%6\n" PPC405_ERR77(0,%3) " stwcx. %1,0,%4\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) Loading Loading
arch/powerpc/include/asm/asm-405.h 0 → 100644 +19 −0 Original line number Diff line number Diff line #ifndef _ASM_POWERPC_ASM_405_H #define _ASM_POWERPC_ASM_405_H #include <asm/asm-const.h> #ifdef __KERNEL__ #ifdef CONFIG_IBM405_ERR77 /* Erratum #77 on the 405 means we need a sync or dcbt before every * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this. */ #define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;) #define PPC405_ERR77_SYNC stringify_in_c(sync;) #else #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif #endif #endif /* _ASM_POWERPC_ASM_405_H */
arch/powerpc/include/asm/asm-compat.h +0 −13 Original line number Diff line number Diff line Loading @@ -70,17 +70,4 @@ #endif #ifdef __KERNEL__ #ifdef CONFIG_IBM405_ERR77 /* Erratum #77 on the 405 means we need a sync or dcbt before every * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this. */ #define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;) #define PPC405_ERR77_SYNC stringify_in_c(sync;) #else #define PPC405_ERR77(ra,rb) #define PPC405_ERR77_SYNC #endif #endif #endif /* _ASM_POWERPC_ASM_COMPAT_H */
arch/powerpc/include/asm/atomic.h +1 −0 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ #include <linux/types.h> #include <asm/cmpxchg.h> #include <asm/barrier.h> #include <asm/asm-405.h> #define ATOMIC_INIT(i) { (i) } Loading
arch/powerpc/include/asm/bitops.h +1 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,7 @@ #include <linux/compiler.h> #include <asm/asm-compat.h> #include <asm/synch.h> #include <asm/asm-405.h> /* PPC bit number conversion */ #define PPC_BITLSHIFT(be) (BITS_PER_LONG - 1 - (be)) Loading
arch/powerpc/include/asm/book3s/32/pgtable.h +0 −2 Original line number Diff line number Diff line Loading @@ -164,7 +164,6 @@ static inline unsigned long pte_update(pte_t *p, 1: lwarx %0,0,%3\n\ andc %1,%0,%4\n\ or %1,%1,%5\n" PPC405_ERR77(0,%3) " stwcx. %1,0,%3\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) Loading @@ -186,7 +185,6 @@ static inline unsigned long long pte_update(pte_t *p, lwzx %0,0,%3\n\ andc %1,%L0,%5\n\ or %1,%1,%6\n" PPC405_ERR77(0,%3) " stwcx. %1,0,%4\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) Loading