Commit 364ac786 authored by Radhakrishna Sripada's avatar Radhakrishna Sripada Committed by Jani Nikula
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drm/i915/mtl: Fix Wa_16015201720 implementation 



The commit 2357f2b2 ("drm/i915/mtl: Initial display workarounds")
extended the workaround Wa_16015201720 to MTL. However the registers
that the original WA implemented moved for MTL.

Implement the workaround with the correct register.

v3: Skip clock gating for pipe C, D DMC's and fix the title

Fixes: 2357f2b2 ("drm/i915/mtl: Initial display workarounds")
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-2-radhakrishna.sripada@intel.com


(cherry picked from commit 0188be50)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent e8d018dd

drivers/gpu/drm/i915/display/intel_dmc.c

+21 −5
Original line number Diff line number Diff line
@@ -384,15 +384,12 @@ static void disable_all_event_handlers(struct drm_i915_private *i915) 
	}

}



static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)

static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)

{

	enum pipe pipe;



	if (DISPLAY_VER(i915) < 13)

		return;



	/*

	 * Wa_16015201720:adl-p,dg2, mtl

	 * Wa_16015201720:adl-p,dg2

	 * The WA requires clock gating to be disabled all the time

	 * for pipe A and B.

	 * For pipe C and D clock gating needs to be disabled only
@@ -408,6 +405,25 @@ static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) 
				     PIPEDMC_GATING_DIS, 0);

}



static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915)

{

	/*

	 * Wa_16015201720

	 * The WA requires clock gating to be disabled all the time

	 * for pipe A and B.

	 */

	intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0,

		     MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B);

}



static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable)

{

	if (DISPLAY_VER(i915) >= 14 && enable)

		mtl_pipedmc_clock_gating_wa(i915);

	else if (DISPLAY_VER(i915) == 13)

		adlp_pipedmc_clock_gating_wa(i915, enable);

}



void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe)

{

	if (!has_dmc_id_fw(i915, PIPE_TO_DMC_ID(pipe)))

drivers/gpu/drm/i915/i915_reg.h

+5 −3
Original line number Diff line number Diff line
@@ -1786,9 +1786,11 @@ 
 * GEN9 clock gating regs

 */

#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)

#define   DARBF_GATING_DIS		(1 << 27)

#define   PWM2_GATING_DIS		(1 << 14)

#define   PWM1_GATING_DIS		(1 << 13)

#define   DARBF_GATING_DIS		REG_BIT(27)

#define   MTL_PIPEDMC_GATING_DIS_A	REG_BIT(15)

#define   MTL_PIPEDMC_GATING_DIS_B	REG_BIT(14)

#define   PWM2_GATING_DIS		REG_BIT(14)

#define   PWM1_GATING_DIS		REG_BIT(13)



#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)

#define   TGL_VRH_GATING_DIS		REG_BIT(31)