Commit 364a5a8a authored by Will Deacon's avatar Will Deacon
Browse files

arm64: cpufeatures: Add capability for LDAPR instruction



Armv8.3 introduced the LDAPR instruction, which provides weaker memory
ordering semantics than LDARi (RCpc vs RCsc). Generally, we provide an
RCsc implementation when implementing the Linux memory model, but LDAPR
can be used as a useful alternative to dependency ordering, particularly
when the compiler is capable of breaking the dependencies.

Since LDAPR is not available on all CPUs, add a cpufeature to detect it at
runtime and allow the instruction to be used with alternative code
patching.

Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 7cda23da
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+3 −0
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@@ -1388,6 +1388,9 @@ config ARM64_PAN
	 The feature is detected at runtime, and will remain as a 'nop'
	 instruction if the cpu does not implement the feature.

config AS_HAS_LDAPR
	def_bool $(as-instr,.arch_extension rcpc)

config ARM64_LSE_ATOMICS
	bool
	default ARM64_USE_LSE_ATOMICS
+2 −1
Original line number Diff line number Diff line
@@ -66,7 +66,8 @@
#define ARM64_HAS_TLB_RANGE			56
#define ARM64_MTE				57
#define ARM64_WORKAROUND_1508412		58
#define ARM64_HAS_LDAPR				59

#define ARM64_NCAPS				59
#define ARM64_NCAPS				60

#endif /* __ASM_CPUCAPS_H */
+10 −0
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@@ -2136,6 +2136,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
		.cpu_enable = cpu_enable_mte,
	},
#endif /* CONFIG_ARM64_MTE */
	{
		.desc = "RCpc load-acquire (LDAPR)",
		.capability = ARM64_HAS_LDAPR,
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
		.sys_reg = SYS_ID_AA64ISAR1_EL1,
		.sign = FTR_UNSIGNED,
		.field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
		.matches = has_cpuid_feature,
		.min_field_value = 1,
	},
	{},
};