Commit 36289a03 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'v6.3-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 

Pull crypto update from Herbert Xu:
 "API:
   - Use kmap_local instead of kmap_atomic
   - Change request callback to take void pointer
   - Print FIPS status in /proc/crypto (when enabled)

  Algorithms:
   - Add rfc4106/gcm support on arm64
   - Add ARIA AVX2/512 support on x86

  Drivers:
   - Add TRNG driver for StarFive SoC
   - Delete ux500/hash driver (subsumed by stm32/hash)
   - Add zlib support in qat
   - Add RSA support in aspeed"

* tag 'v6.3-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (156 commits)
  crypto: x86/aria-avx - Do not use avx2 instructions
  crypto: aspeed - Fix modular aspeed-acry
  crypto: hisilicon/qm - fix coding style issues
  crypto: hisilicon/qm - update comments to match function
  crypto: hisilicon/qm - change function names
  crypto: hisilicon/qm - use min() instead of min_t()
  crypto: hisilicon/qm - remove some unused defines
  crypto: proc - Print fips status
  crypto: crypto4xx - Call dma_unmap_page when done
  crypto: octeontx2 - Fix objects shared between several modules
  crypto: nx - Fix sparse warnings
  crypto: ecc - Silence sparse warning
  tls: Pass rec instead of aead_req into tls_encrypt_done
  crypto: api - Remove completion function scaffolding
  tls: Remove completion function scaffolding
  tipc: Remove completion function scaffolding
  net: ipv6: Remove completion function scaffolding
  net: ipv4: Remove completion function scaffolding
  net: macsec: Remove completion function scaffolding
  dm: Remove completion function scaffolding
  ...
parents 69308402 8b844753

Documentation/ABI/testing/sysfs-driver-qat

+2 −2
Original line number Diff line number Diff line 
What:		/sys/bus/pci/devices/<BDF>/qat/state

Date:		June 2022

KernelVersion:	5.20

KernelVersion:	6.0

Contact:	qat-linux@intel.com

Description:	(RW) Reports the current state of the QAT device. Write to

		the file to start or stop the device.
@@ -18,7 +18,7 @@ Description: (RW) Reports the current state of the QAT device. Write to 


What:		/sys/bus/pci/devices/<BDF>/qat/cfg_services

Date:		June 2022

KernelVersion:	5.20

KernelVersion:	6.0

Contact:	qat-linux@intel.com

Description:	(RW) Reports the current configuration of the QAT device.

		Write to the file to change the configured services.

Documentation/devicetree/bindings/bus/aspeed,ast2600-ahbc.yaml

0 → 100644
+37 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/bus/aspeed,ast2600-ahbc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ASPEED Advanced High-Performance Bus Controller (AHBC)



maintainers:

  - Neal Liu <neal_liu@aspeedtech.com>

  - Chia-Wei Wang <chiawei_wang@aspeedtech.com>



description: |

  Advanced High-performance Bus Controller (AHBC) supports plenty of mechanisms

  including a priority arbiter, an address decoder and a data multiplexer

  to control the overall operations of Advanced High-performance Bus (AHB).



properties:

  compatible:

    enum:

      - aspeed,ast2600-ahbc



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    ahbc@1e600000 {

        compatible = "aspeed,ast2600-ahbc";

        reg = <0x1e600000 0x100>;

    };

Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml

+25 −8
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ properties: 
    enum:

      - allwinner,sun8i-h3-crypto

      - allwinner,sun8i-r40-crypto

      - allwinner,sun20i-d1-crypto

      - allwinner,sun50i-a64-crypto

      - allwinner,sun50i-h5-crypto

      - allwinner,sun50i-h6-crypto
@@ -29,6 +30,7 @@ properties: 
      - description: Bus clock

      - description: Module clock

      - description: MBus clock

      - description: TRNG clock (RC oscillator)

    minItems: 2



  clock-names:
@@ -36,11 +38,24 @@ properties: 
      - const: bus

      - const: mod

      - const: ram

      - const: trng

    minItems: 2



  resets:

    maxItems: 1



if:

  properties:

    compatible:

      enum:

        - allwinner,sun20i-d1-crypto

then:

  properties:

    clocks:

      minItems: 4

    clock-names:

      minItems: 4

else:

  if:

    properties:

      compatible:
@@ -49,8 +64,10 @@ then: 
    properties:

      clocks:

        minItems: 3

        maxItems: 3

      clock-names:

        minItems: 3

        maxItems: 3

  else:

    properties:

      clocks:

Documentation/devicetree/bindings/crypto/aspeed,ast2600-acry.yaml

0 → 100644
+49 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/crypto/aspeed,ast2600-acry.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines



maintainers:

  - Neal Liu <neal_liu@aspeedtech.com>



description:

  The ACRY ECDSA/RSA engines is designed to accelerate the throughput

  of ECDSA/RSA signature and verification. Basically, ACRY can be

  divided into two independent engines - ECC Engine and RSA Engine.



properties:

  compatible:

    enum:

      - aspeed,ast2600-acry



  reg:

    items:

      - description: acry base address & size

      - description: acry sram base address & size



  clocks:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/ast2600-clock.h>

    acry: crypto@1e6fa000 {

        compatible = "aspeed,ast2600-acry";

        reg = <0x1e6fa000 0x400>, <0x1e710000 0x1800>;

        interrupts = <160>;

        clocks = <&syscon ASPEED_CLK_GATE_RSACLK>;

    };

Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml

+22 −1
Original line number Diff line number Diff line
@@ -6,12 +6,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# 


title: STMicroelectronics STM32 HASH



description: The STM32 HASH block is built on the HASH block found in

  the STn8820 SoC introduced in 2007, and subsequently used in the U8500

  SoC in 2010.



maintainers:

  - Lionel Debieve <lionel.debieve@foss.st.com>



properties:

  compatible:

    enum:

      - st,stn8820-hash

      - stericsson,ux500-hash

      - st,stm32f456-hash

      - st,stm32f756-hash
@@ -41,10 +47,25 @@ properties: 
    maximum: 2

    default: 0



  power-domains:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks



allOf:

  - if:

      properties:

        compatible:

          items:

            const: stericsson,ux500-hash

    then:

      properties:

        interrupts: false

    else:

      required:

        - interrupts



additionalProperties: false