dt-bindings: net: convert qca,ar71xx documentation to yaml (3608a199) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/net/qca,ar71xx.txt

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		Required properties:
		- compatible: Should be "qca,<soc>-eth". Currently support compatibles are:
		qca,ar7100-eth - Atheros AR7100
		qca,ar7240-eth - Atheros AR7240
		qca,ar7241-eth - Atheros AR7241
		qca,ar7242-eth - Atheros AR7242
		qca,ar9130-eth - Atheros AR9130
		qca,ar9330-eth - Atheros AR9330
		qca,ar9340-eth - Atheros AR9340
		qca,qca9530-eth - Qualcomm Atheros QCA9530
		qca,qca9550-eth - Qualcomm Atheros QCA9550
		qca,qca9560-eth - Qualcomm Atheros QCA9560

		- reg : Address and length of the register set for the device
		- interrupts : Should contain eth interrupt
		- phy-mode : See ethernet.txt file in the same directory
		- clocks: the clock used by the core
		- clock-names: the names of the clock listed in the clocks property. These are
		"eth" and "mdio".
		- resets: Should contain phandles to the reset signals
		- reset-names: Should contain the names of reset signal listed in the resets
		property. These are "mac" and "mdio"

		Optional properties:
		- phy-handle : phandle to the PHY device connected to this device.
		- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
		Use instead of phy-handle.

		Optional subnodes:
		- mdio : specifies the mdio bus, used as a container for phy nodes
		according to phy.txt in the same directory

		Example:

		ethernet@1a000000 {
		compatible = "qca,ar9330-eth";
		reg = <0x1a000000 0x200>;
		interrupts = <5>;
		resets = <&rst 13>, <&rst 23>;
		reset-names = "mac", "mdio";
		clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_MDIO>;
		clock-names = "eth", "mdio";

		phy-mode = "gmii";
		};

Documentation/devicetree/bindings/net/qca,ar71xx.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: QCA AR71XX MAC

		allOf:
		- $ref: ethernet-controller.yaml#

		maintainers:
		- Oleksij Rempel <o.rempel@pengutronix.de>

		properties:
		compatible:
		oneOf:
		- items:
		- enum:
		- qca,ar7100-eth # Atheros AR7100
		- qca,ar7240-eth # Atheros AR7240
		- qca,ar7241-eth # Atheros AR7241
		- qca,ar7242-eth # Atheros AR7242
		- qca,ar9130-eth # Atheros AR9130
		- qca,ar9330-eth # Atheros AR9330
		- qca,ar9340-eth # Atheros AR9340
		- qca,qca9530-eth # Qualcomm Atheros QCA9530
		- qca,qca9550-eth # Qualcomm Atheros QCA9550
		- qca,qca9560-eth # Qualcomm Atheros QCA9560

		reg:
		maxItems: 1

		interrupts:
		maxItems: 1

		'#address-cells':
		description: number of address cells for the MDIO bus
		const: 1

		'#size-cells':
		description: number of size cells on the MDIO bus
		const: 0

		clocks:
		items:
		- description: MAC main clock
		- description: MDIO clock

		clock-names:
		items:
		- const: eth
		- const: mdio

		resets:
		items:
		- description: MAC reset
		- description: MDIO reset

		reset-names:
		items:
		- const: mac
		- const: mdio

		required:
		- compatible
		- reg
		- interrupts
		- phy-mode
		- clocks
		- clock-names
		- resets
		- reset-names

		examples:
		# Lager board
		- \|
		eth0: ethernet@19000000 {
		compatible = "qca,ar9330-eth";
		reg = <0x19000000 0x200>;
		interrupts = <4>;
		resets = <&rst 9>, <&rst 22>;
		reset-names = "mac", "mdio";
		clocks = <&pll 1>, <&pll 2>;
		clock-names = "eth", "mdio";
		qca,ethcfg = <&ethcfg>;
		phy-mode = "mii";
		phy-handle = <&phy_port4>;
		};

		eth1: ethernet@1a000000 {
		compatible = "qca,ar9330-eth";
		reg = <0x1a000000 0x200>;
		interrupts = <5>;
		resets = <&rst 13>, <&rst 23>;
		reset-names = "mac", "mdio";
		clocks = <&pll 1>, <&pll 2>;
		clock-names = "eth", "mdio";

		phy-mode = "gmii";

		status = "disabled";

		fixed-link {
		speed = <1000>;
		full-duplex;
		};

		mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		switch10: switch@10 {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qca,ar9331-switch";
		reg = <0x10>;
		resets = <&rst 8>;
		reset-names = "switch";

		interrupt-parent = <&miscintc>;
		interrupts = <12>;

		interrupt-controller;
		#interrupt-cells = <1>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		switch_port0: port@0 {
		reg = <0x0>;
		label = "cpu";
		ethernet = <&eth1>;

		phy-mode = "gmii";

		fixed-link {
		speed = <1000>;
		full-duplex;
		};
		};

		switch_port1: port@1 {
		reg = <0x1>;
		phy-handle = <&phy_port0>;
		phy-mode = "internal";

		status = "disabled";
		};

		switch_port2: port@2 {
		reg = <0x2>;
		phy-handle = <&phy_port1>;
		phy-mode = "internal";

		status = "disabled";
		};

		switch_port3: port@3 {
		reg = <0x3>;
		phy-handle = <&phy_port2>;
		phy-mode = "internal";

		status = "disabled";
		};

		switch_port4: port@4 {
		reg = <0x4>;
		phy-handle = <&phy_port3>;
		phy-mode = "internal";

		status = "disabled";
		};
		};

		mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		interrupt-parent = <&switch10>;

		phy_port0: phy@0 {
		reg = <0x0>;
		interrupts = <0>;
		status = "disabled";
		};

		phy_port1: phy@1 {
		reg = <0x1>;
		interrupts = <0>;
		status = "disabled";
		};

		phy_port2: phy@2 {
		reg = <0x2>;
		interrupts = <0>;
		status = "disabled";
		};

		phy_port3: phy@3 {
		reg = <0x3>;
		interrupts = <0>;
		status = "disabled";
		};

		phy_port4: phy@4 {
		reg = <0x4>;
		interrupts = <0>;
		status = "disabled";
		};
		};
		};
		};
		};