Commit 35f5ace5 authored by Devesh Sharma's avatar Devesh Sharma Committed by Jason Gunthorpe
Browse files

RDMA/bnxt_re: Enable global atomic ops if platform supports 

Enabling Atomic operations for Gen P5 devices if the underlying platform
supports global atomic ops.

Link: https://lore.kernel.org/r/20210603131534.982257-2-devesh.sharma@broadcom.com


Signed-off-by: default avatarDevesh Sharma <devesh.sharma@broadcom.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 32a25f2e

drivers/infiniband/hw/bnxt_re/ib_verbs.c

+4 −0
Original line number Diff line number Diff line
@@ -163,6 +163,10 @@ int bnxt_re_query_device(struct ib_device *ibdev, 
	ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;

	ib_attr->atomic_cap = IB_ATOMIC_NONE;

	ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;

	if (dev_attr->is_atomic) {

		ib_attr->atomic_cap = IB_ATOMIC_GLOB;

		ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;

	}



	ib_attr->max_ee_rd_atom = 0;

	ib_attr->max_res_rd_atom = 0;

drivers/infiniband/hw/bnxt_re/main.c

+3 −0
Original line number Diff line number Diff line
@@ -128,6 +128,9 @@ static int bnxt_re_setup_chip_ctx(struct bnxt_re_dev *rdev, u8 wqe_mode) 
	rdev->rcfw.res = &rdev->qplib_res;



	bnxt_re_set_drv_mode(rdev, wqe_mode);

	if (bnxt_qplib_determine_atomics(en_dev->pdev))

		ibdev_info(&rdev->ibdev,

			   "platform doesn't support global atomics.");

	return 0;

}

drivers/infiniband/hw/bnxt_re/qplib_res.c

+17 −0
Original line number Diff line number Diff line
@@ -959,3 +959,20 @@ int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev, 
	bnxt_qplib_free_res(res);

	return rc;

}



int bnxt_qplib_determine_atomics(struct pci_dev *dev)

{

	int comp;

	u16 ctl2;



	comp = pci_enable_atomic_ops_to_root(dev,

					     PCI_EXP_DEVCAP2_ATOMIC_COMP32);

	if (comp)

		return -EOPNOTSUPP;

	comp = pci_enable_atomic_ops_to_root(dev,

					     PCI_EXP_DEVCAP2_ATOMIC_COMP64);

	if (comp)

		return -EOPNOTSUPP;

	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctl2);

	return !(ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);

}

drivers/infiniband/hw/bnxt_re/qplib_res.h

+1 −0
Original line number Diff line number Diff line
@@ -373,6 +373,7 @@ void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res, 
int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,

			 struct bnxt_qplib_ctx *ctx,

			 bool virt_fn, bool is_p5);

int bnxt_qplib_determine_atomics(struct pci_dev *dev);



static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)

{

drivers/infiniband/hw/bnxt_re/qplib_sp.c

+12 −1
Original line number Diff line number Diff line
@@ -54,6 +54,17 @@ const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 


/* Device */



static bool bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw)

{

	u16 pcie_ctl2 = 0;



	if (!bnxt_qplib_is_chip_gen_p5(rcfw->res->cctx))

		return false;



	pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2);

	return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ);

}



static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw,

				     char *fw_ver)

{
@@ -162,7 +173,7 @@ int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw, 
		attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc);

	}



	attr->is_atomic = false;

	attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw);

bail:

	bnxt_qplib_rcfw_free_sbuf(rcfw, sbuf);

	return rc;