Commit 35cf1aaa authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes 



Add UFS host controller and PHY nodes.

Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230116141000.1831351-1-abel.vesa@linaro.org
parent 2f20f276

arch/arm64/boot/dts/qcom/sm8550.dtsi

+70 −3
Original line number Diff line number Diff line
@@ -649,9 +649,9 @@ 
				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <0>,

				 <&ufs_mem_phy 0>,

				 <&ufs_mem_phy 1>,

				 <&ufs_mem_phy 2>,

				 <0>;

		};
@@ -1571,6 +1571,73 @@ 
			interconnect-names = "memory";

		};



		ufs_mem_phy: phy@1d80000 {

			compatible = "qcom,sm8550-qmp-ufs-phy";

			reg = <0x0 0x01d80000 0x0 0x2000>;

			clocks = <&tcsr TCSR_UFS_CLKREF_EN>,

				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

			clock-names = "ref", "ref_aux";



			power-domains = <&gcc UFS_MEM_PHY_GDSC>;



			resets = <&ufs_mem_hc 0>;

			reset-names = "ufsphy";



			#clock-cells = <1>;

			#phy-cells = <0>;



			status = "disabled";

		};



		ufs_mem_hc: ufs@1d84000 {

			compatible = "qcom,sm8550-ufshc", "qcom,ufshc",

				     "jedec,ufs-2.0";

			reg = <0x0 0x01d84000 0x0 0x3000>;

			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&ufs_mem_phy>;

			phy-names = "ufsphy";

			lanes-per-direction = <2>;

			#reset-cells = <1>;

			resets = <&gcc GCC_UFS_PHY_BCR>;

			reset-names = "rst";



			power-domains = <&gcc UFS_PHY_GDSC>;

			required-opps = <&rpmhpd_opp_nom>;



			iommus = <&apps_smmu 0x60 0x0>;



			interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,

					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;



			interconnect-names = "ufs-ddr", "cpu-ufs";

			clock-names = "core_clk",

				      "bus_aggr_clk",

				      "iface_clk",

				      "core_clk_unipro",

				      "ref_clk",

				      "tx_lane0_sync_clk",

				      "rx_lane0_sync_clk",

				      "rx_lane1_sync_clk";

			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

				 <&gcc GCC_UFS_PHY_AHB_CLK>,

				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

				 <&tcsr TCSR_UFS_PAD_CLKREF_EN>,

				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

			freq-table-hz =

				<75000000 300000000>,

				<0 0>,

				<0 0>,

				<75000000 300000000>,

				<100000000 403000000>,

				<0 0>,

				<0 0>,

				<0 0>;

			status = "disabled";

		};



		tcsr_mutex: hwlock@1f40000 {

			compatible = "qcom,tcsr-mutex";

			reg = <0 0x01f40000 0 0x20000>;