Commit 359f10c1 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g044: Add M3 Clock support 



Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 300d95c5

drivers/clk/renesas/r9a07g044-cpg.c

+4 −1
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ enum clk_ids { 
	CLK_SD1_DIV4,

	CLK_SEL_GPU2,

	CLK_SEL_PLL5_4,

	CLK_DSI_DIV,



	/* Module Clocks */

	MOD_CLK_BASE,
@@ -87,7 +88,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" }; 
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };



static const struct {

	struct cpg_core_clk common[50];

	struct cpg_core_clk common[52];

#ifdef CONFIG_CLK_R9A07G054

	struct cpg_core_clk drp[0];

#endif
@@ -166,6 +167,8 @@ static const struct { 
		DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),

		DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),

		DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),

		DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),

		DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),

	},

#ifdef CONFIG_CLK_R9A07G054

	.drp = {