Unverified Commit 359ae7fe authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!10893 [openEuler-24.03-LTS][linux-6.6.y sync] Backport 6.6.45 LTS Patches 

Merge Pull Request from: @anred 
 
```
git log --oneline v6.6.44..v6.6.45 | wc -l
121
```
8 + 4 + 109 = 121

Merged(8)
```
 mptcp: prevent BPF accessing lowat from a subflow socket.
 mptcp: give rcvlowat some love
 mm: page_alloc: control latency caused by zone PCP draining
 mm: restrict the pcp batch scale factor to avoid too long latency
 ext4: check the extent status again before inserting delalloc block
 ext4: factor out a common helper to query extent map
 ext4: convert to exclusive lock while inserting delalloc extents
 ext4: refactor ext4_da_map_blocks()
```
Conflicts(4)
```
 Linux 6.6.45
 rust: SHADOW_CALL_STACK is incompatible with Rust
 sysctl: always initialize i_uid/i_gid
 sysctl: treewide: drop unused argument ctl_table_root::set_ownership(table)
``` 
 
Link:https://gitee.com/openeuler/kernel/pulls/10893

 

Reviewed-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parents a151658a 08676a49

arch/arm/kernel/perf_callchain.c

+1 −2
Original line number Diff line number Diff line
@@ -85,8 +85,7 @@ static bool 
callchain_trace(void *data, unsigned long pc)

{

	struct perf_callchain_entry_ctx *entry = data;

	perf_callchain_store(entry, pc);

	return true;

	return perf_callchain_store(entry, pc) == 0;

}



void

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -641,6 +641,7 @@ 
				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;

				phys = <&qusb_phy_0>, <&usb0_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

				snps,parkmode-disable-ss-quirk;

				snps,is-utmi-l1-suspend;

				snps,hird-threshold = /bits/ 8 <0x0>;

				snps,dis_u2_susphy_quirk;
@@ -683,6 +684,7 @@ 
				interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;

				phys = <&qusb_phy_1>, <&usb1_ssphy>;

				phy-names = "usb2-phy", "usb3-phy";

				snps,parkmode-disable-ss-quirk;

				snps,is-utmi-l1-suspend;

				snps,hird-threshold = /bits/ 8 <0x0>;

				snps,dis_u2_susphy_quirk;

arch/arm64/boot/dts/qcom/msm8998.dtsi

+15 −21
Original line number Diff line number Diff line
@@ -2159,7 +2159,8 @@ 
				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&qusb2phy>, <&usb1_ssphy>;

				snps,parkmode-disable-ss-quirk;

				phys = <&qusb2phy>, <&usb3phy>;

				phy-names = "usb2-phy", "usb3-phy";

				snps,has-lpm-erratum;

				snps,hird-threshold = /bits/ 8 <0x10>;
@@ -2168,33 +2169,26 @@ 


		usb3phy: phy@c010000 {

			compatible = "qcom,msm8998-qmp-usb3-phy";

			reg = <0x0c010000 0x18c>;

			status = "disabled";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			reg = <0x0c010000 0x1000>;



			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,

				 <&gcc GCC_USB3_CLKREF_CLK>,

				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

				 <&gcc GCC_USB3_CLKREF_CLK>;

			clock-names = "aux", "cfg_ahb", "ref";

				 <&gcc GCC_USB3_PHY_PIPE_CLK>;

			clock-names = "aux",

				      "ref",

				      "cfg_ahb",

				      "pipe";

			clock-output-names = "usb3_phy_pipe_clk_src";

			#clock-cells = <0>;

			#phy-cells = <0>;



			resets = <&gcc GCC_USB3_PHY_BCR>,

				 <&gcc GCC_USB3PHY_PHY_BCR>;

			reset-names = "phy", "common";

			reset-names = "phy",

				      "phy_phy";



			usb1_ssphy: phy@c010200 {

				reg = <0xc010200 0x128>,

				      <0xc010400 0x200>,

				      <0xc010c00 0x20c>,

				      <0xc010600 0x128>,

				      <0xc010800 0x200>;

				#phy-cells = <0>;

				#clock-cells = <0>;

				clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};

			status = "disabled";

		};



		qusb2phy: phy@c012000 {

arch/arm64/boot/dts/qcom/sc7180.dtsi

+20 −38
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 
#include <dt-bindings/interconnect/qcom,osm-l3.h>

#include <dt-bindings/interconnect/qcom,sc7180.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/phy/phy-qcom-qmp.h>

#include <dt-bindings/phy/phy-qcom-qusb2.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/reset/qcom,sdm845-aoss.h>
@@ -2795,49 +2796,28 @@ 
			nvmem-cells = <&qusb2p_hstx_trim>;

		};



		usb_1_qmpphy: phy-wrapper@88e9000 {

		usb_1_qmpphy: phy@88e8000 {

			compatible = "qcom,sc7180-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x18c>,

			      <0 0x088e8000 0 0x3c>,

			      <0 0x088ea000 0 0x18c>;

			reg = <0 0x088e8000 0 0x3000>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "cfg_ahb", "ref", "com_aux";

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,

				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;

			clock-names = "aux",

				      "ref",

				      "com_aux",

				      "usb3_pipe",

				      "cfg_ahb";



			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x128>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x218>,

				      <0 0x088e9600 0 0x128>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x18>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eaa00 0 0x200>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>;

			#clock-cells = <1>;

				#phy-cells = <0>;

			};

			#phy-cells = <1>;

		};



		pmu@90b6300 {
@@ -3001,7 +2981,8 @@ 
				iommus = <&apps_smmu 0x540 0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				snps,parkmode-disable-ss-quirk;

				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;

				phy-names = "usb2-phy", "usb3-phy";

				maximum-speed = "super-speed";

			};
@@ -3307,8 +3288,9 @@ 
					      "ctrl_link_iface", "stream_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;

				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

				phys = <&dp_phy>;

				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

				phy-names = "dp";



				operating-points-v2 = <&dp_opp_table>;
@@ -3365,8 +3347,8 @@ 
				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,

				 <&mdss_dsi0_phy 0>,

				 <&mdss_dsi0_phy 1>,

				 <&dp_phy 0>,

				 <&dp_phy 1>;

				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

			clock-names = "bi_tcxo",

				      "gcc_disp_gpll0_clk_src",

				      "dsi0_phy_pll_out_byteclk",

arch/arm64/boot/dts/qcom/sc7280.dtsi

+20 −40
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <dt-bindings/interconnect/qcom,sc7280.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/mailbox/qcom-ipcc.h>

#include <dt-bindings/phy/phy-qcom-qmp.h>

#include <dt-bindings/power/qcom-rpmpd.h>

#include <dt-bindings/reset/qcom,sdm845-aoss.h>

#include <dt-bindings/reset/qcom,sdm845-pdc.h>
@@ -858,7 +859,7 @@ 
				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,

				 <0>, <&pcie1_lane>,

				 <0>, <0>, <0>,

				 <&usb_1_ssphy>;

				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;

			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",

				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",

				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
@@ -3351,49 +3352,26 @@ 
			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;

		};



		usb_1_qmpphy: phy-wrapper@88e9000 {

			compatible = "qcom,sc7280-qmp-usb3-dp-phy",

				     "qcom,sm8250-qmp-usb3-dp-phy";

			reg = <0 0x088e9000 0 0x200>,

			      <0 0x088e8000 0 0x40>,

			      <0 0x088ea000 0 0x200>;

		usb_1_qmpphy: phy@88e8000 {

			compatible = "qcom,sc7280-qmp-usb3-dp-phy";

			reg = <0 0x088e8000 0 0x3000>;

			status = "disabled";

			#address-cells = <2>;

			#size-cells = <2>;

			ranges;



			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,

				 <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;

			clock-names = "aux", "ref_clk_src", "com_aux";

				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,

				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

			clock-names = "aux",

				      "ref",

				      "com_aux",

				      "usb3_pipe";



			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,

				 <&gcc GCC_USB3_PHY_PRIM_BCR>;

			reset-names = "phy", "common";



			usb_1_ssphy: usb3-phy@88e9200 {

				reg = <0 0x088e9200 0 0x200>,

				      <0 0x088e9400 0 0x200>,

				      <0 0x088e9c00 0 0x400>,

				      <0 0x088e9600 0 0x200>,

				      <0 0x088e9800 0 0x200>,

				      <0 0x088e9a00 0 0x100>;

				#clock-cells = <0>;

				#phy-cells = <0>;

				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

				clock-names = "pipe0";

				clock-output-names = "usb3_phy_pipe_clk_src";

			};



			dp_phy: dp-phy@88ea200 {

				reg = <0 0x088ea200 0 0x200>,

				      <0 0x088ea400 0 0x200>,

				      <0 0x088eaa00 0 0x200>,

				      <0 0x088ea600 0 0x200>,

				      <0 0x088ea800 0 0x200>;

				#phy-cells = <0>;

			#clock-cells = <1>;

			};

			#phy-cells = <1>;

		};



		usb_2: usb@8cf8800 {
@@ -3702,7 +3680,8 @@ 
				iommus = <&apps_smmu 0xe0 0x0>;

				snps,dis_u2_susphy_quirk;

				snps,dis_enblslpm_quirk;

				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;

				snps,parkmode-disable-ss-quirk;

				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;

				phy-names = "usb2-phy", "usb3-phy";

				maximum-speed = "super-speed";

			};
@@ -3807,8 +3786,8 @@ 
				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,

				 <&mdss_dsi_phy 0>,

				 <&mdss_dsi_phy 1>,

				 <&dp_phy 0>,

				 <&dp_phy 1>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,

				 <&mdss_edp_phy 0>,

				 <&mdss_edp_phy 1>;

			clock-names = "bi_tcxo",
@@ -4144,8 +4123,9 @@ 
						"stream_pixel";

				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,

						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;

				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;

				phys = <&dp_phy>;

				assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,

							 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

				phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;

				phy-names = "dp";



				operating-points-v2 = <&dp_opp_table>;