Commit 35878142 authored by Alexander Shiyan's avatar Alexander Shiyan Committed by Shawn Guo
Browse files

ARM: dts: i.MX51: Move pins configuration under "iomuxc" label 



This unmix module/pin definitions and reduce indentation for pin
groups, so makes template a bit cleaner.

Signed-off-by: default avatarAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent e3c68c86

arch/arm/boot/dts/imx51.dtsi

+309 −307
Original line number Diff line number Diff line
@@ -308,7 +308,202 @@ 
			iomuxc: iomuxc@73fa8000 {

				compatible = "fsl,imx51-iomuxc";

				reg = <0x73fa8000 0x4000>;

			};



			pwm1: pwm@73fb4000 {

				#pwm-cells = <2>;

				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";

				reg = <0x73fb4000 0x4000>;

				clocks = <&clks 37>, <&clks 38>;

				clock-names = "ipg", "per";

				interrupts = <61>;

			};



			pwm2: pwm@73fb8000 {

				#pwm-cells = <2>;

				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";

				reg = <0x73fb8000 0x4000>;

				clocks = <&clks 39>, <&clks 40>;

				clock-names = "ipg", "per";

				interrupts = <94>;

			};



			uart1: serial@73fbc000 {

				compatible = "fsl,imx51-uart", "fsl,imx21-uart";

				reg = <0x73fbc000 0x4000>;

				interrupts = <31>;

				clocks = <&clks 28>, <&clks 29>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			uart2: serial@73fc0000 {

				compatible = "fsl,imx51-uart", "fsl,imx21-uart";

				reg = <0x73fc0000 0x4000>;

				interrupts = <32>;

				clocks = <&clks 30>, <&clks 31>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			src: src@73fd0000 {

				compatible = "fsl,imx51-src";

				reg = <0x73fd0000 0x4000>;

				#reset-cells = <1>;

			};



			clks: ccm@73fd4000{

				compatible = "fsl,imx51-ccm";

				reg = <0x73fd4000 0x4000>;

				interrupts = <0 71 0x04 0 72 0x04>;

				#clock-cells = <1>;

			};

		};



		aips@80000000 {	/* AIPS2 */

			compatible = "fsl,aips-bus", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x80000000 0x10000000>;

			ranges;



			iim: iim@83f98000 {

				compatible = "fsl,imx51-iim", "fsl,imx27-iim";

				reg = <0x83f98000 0x4000>;

				interrupts = <69>;

				clocks = <&clks 107>;

			};



			ecspi2: ecspi@83fac000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-ecspi";

				reg = <0x83fac000 0x4000>;

				interrupts = <37>;

				clocks = <&clks 53>, <&clks 54>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			sdma: sdma@83fb0000 {

				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";

				reg = <0x83fb0000 0x4000>;

				interrupts = <6>;

				clocks = <&clks 56>, <&clks 56>;

				clock-names = "ipg", "ahb";

				#dma-cells = <3>;

				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

			};



			cspi: cspi@83fc0000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";

				reg = <0x83fc0000 0x4000>;

				interrupts = <38>;

				clocks = <&clks 55>, <&clks 55>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			i2c2: i2c@83fc4000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";

				reg = <0x83fc4000 0x4000>;

				interrupts = <63>;

				clocks = <&clks 35>;

				status = "disabled";

			};



			i2c1: i2c@83fc8000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";

				reg = <0x83fc8000 0x4000>;

				interrupts = <62>;

				clocks = <&clks 34>;

				status = "disabled";

			};



			ssi1: ssi@83fcc000 {

				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";

				reg = <0x83fcc000 0x4000>;

				interrupts = <29>;

				clocks = <&clks 48>;

				dmas = <&sdma 28 0 0>,

				       <&sdma 29 0 0>;

				dma-names = "rx", "tx";

				fsl,fifo-depth = <15>;

				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */

				status = "disabled";

			};



			audmux: audmux@83fd0000 {

				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";

				reg = <0x83fd0000 0x4000>;

				status = "disabled";

			};



			weim: weim@83fda000 {

				#address-cells = <2>;

				#size-cells = <1>;

				compatible = "fsl,imx51-weim";

				reg = <0x83fda000 0x1000>;

				clocks = <&clks 57>;

				ranges = <

					0 0 0xb0000000 0x08000000

					1 0 0xb8000000 0x08000000

					2 0 0xc0000000 0x08000000

					3 0 0xc8000000 0x04000000

					4 0 0xcc000000 0x02000000

					5 0 0xce000000 0x02000000

				>;

				status = "disabled";

			};



			nfc: nand@83fdb000 {

				compatible = "fsl,imx51-nand";

				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;

				interrupts = <8>;

				clocks = <&clks 60>;

				status = "disabled";

			};



			pata: pata@83fe0000 {

				compatible = "fsl,imx51-pata", "fsl,imx27-pata";

				reg = <0x83fe0000 0x4000>;

				interrupts = <70>;

				clocks = <&clks 161>;

				status = "disabled";

			};



			ssi3: ssi@83fe8000 {

				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";

				reg = <0x83fe8000 0x4000>;

				interrupts = <96>;

				clocks = <&clks 50>;

				dmas = <&sdma 46 0 0>,

				       <&sdma 47 0 0>;

				dma-names = "rx", "tx";

				fsl,fifo-depth = <15>;

				fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */

				status = "disabled";

			};



			fec: ethernet@83fec000 {

				compatible = "fsl,imx51-fec", "fsl,imx27-fec";

				reg = <0x83fec000 0x4000>;

				interrupts = <87>;

				clocks = <&clks 42>, <&clks 42>, <&clks 42>;

				clock-names = "ipg", "ahb", "ptp";

				status = "disabled";

			};

		};

	};

};



&iomuxc {

	audmux {

		pinctrl_audmux_1: audmuxgrp-1 {

			fsl,pins = <
@@ -483,8 +678,8 @@ 
				MX51_PAD_DISP2_DAT15__DISP2_DAT15   0x5

				MX51_PAD_DI2_PIN2__DI2_PIN2	    0x5 /* hsync */

				MX51_PAD_DI2_PIN3__DI2_PIN3	    0x5 /* vsync */

							MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5

							MX51_PAD_DI_GP4__DI2_PIN15	    0x5

				MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */

				MX51_PAD_DI_GP4__DI2_PIN15	    0x5 /* DE */

			>;

		};

	};
@@ -616,196 +811,3 @@ 
		};

	};

};
 


			pwm1: pwm@73fb4000 {

				#pwm-cells = <2>;

				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";

				reg = <0x73fb4000 0x4000>;

				clocks = <&clks 37>, <&clks 38>;

				clock-names = "ipg", "per";

				interrupts = <61>;

			};



			pwm2: pwm@73fb8000 {

				#pwm-cells = <2>;

				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";

				reg = <0x73fb8000 0x4000>;

				clocks = <&clks 39>, <&clks 40>;

				clock-names = "ipg", "per";

				interrupts = <94>;

			};



			uart1: serial@73fbc000 {

				compatible = "fsl,imx51-uart", "fsl,imx21-uart";

				reg = <0x73fbc000 0x4000>;

				interrupts = <31>;

				clocks = <&clks 28>, <&clks 29>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			uart2: serial@73fc0000 {

				compatible = "fsl,imx51-uart", "fsl,imx21-uart";

				reg = <0x73fc0000 0x4000>;

				interrupts = <32>;

				clocks = <&clks 30>, <&clks 31>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			src: src@73fd0000 {

				compatible = "fsl,imx51-src";

				reg = <0x73fd0000 0x4000>;

				#reset-cells = <1>;

			};



			clks: ccm@73fd4000{

				compatible = "fsl,imx51-ccm";

				reg = <0x73fd4000 0x4000>;

				interrupts = <0 71 0x04 0 72 0x04>;

				#clock-cells = <1>;

			};

		};



		aips@80000000 {	/* AIPS2 */

			compatible = "fsl,aips-bus", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0x80000000 0x10000000>;

			ranges;



			iim: iim@83f98000 {

				compatible = "fsl,imx51-iim", "fsl,imx27-iim";

				reg = <0x83f98000 0x4000>;

				interrupts = <69>;

				clocks = <&clks 107>;

			};



			ecspi2: ecspi@83fac000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-ecspi";

				reg = <0x83fac000 0x4000>;

				interrupts = <37>;

				clocks = <&clks 53>, <&clks 54>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			sdma: sdma@83fb0000 {

				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";

				reg = <0x83fb0000 0x4000>;

				interrupts = <6>;

				clocks = <&clks 56>, <&clks 56>;

				clock-names = "ipg", "ahb";

				#dma-cells = <3>;

				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";

			};



			cspi: cspi@83fc0000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";

				reg = <0x83fc0000 0x4000>;

				interrupts = <38>;

				clocks = <&clks 55>, <&clks 55>;

				clock-names = "ipg", "per";

				status = "disabled";

			};



			i2c2: i2c@83fc4000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";

				reg = <0x83fc4000 0x4000>;

				interrupts = <63>;

				clocks = <&clks 35>;

				status = "disabled";

			};



			i2c1: i2c@83fc8000 {

				#address-cells = <1>;

				#size-cells = <0>;

				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";

				reg = <0x83fc8000 0x4000>;

				interrupts = <62>;

				clocks = <&clks 34>;

				status = "disabled";

			};



			ssi1: ssi@83fcc000 {

				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";

				reg = <0x83fcc000 0x4000>;

				interrupts = <29>;

				clocks = <&clks 48>;

				dmas = <&sdma 28 0 0>,

				       <&sdma 29 0 0>;

				dma-names = "rx", "tx";

				fsl,fifo-depth = <15>;

				fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */

				status = "disabled";

			};



			audmux: audmux@83fd0000 {

				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";

				reg = <0x83fd0000 0x4000>;

				status = "disabled";

			};



			weim: weim@83fda000 {

				#address-cells = <2>;

				#size-cells = <1>;

				compatible = "fsl,imx51-weim";

				reg = <0x83fda000 0x1000>;

				clocks = <&clks 57>;

				ranges = <

					0 0 0xb0000000 0x08000000

					1 0 0xb8000000 0x08000000

					2 0 0xc0000000 0x08000000

					3 0 0xc8000000 0x04000000

					4 0 0xcc000000 0x02000000

					5 0 0xce000000 0x02000000

				>;

				status = "disabled";

			};



			nfc: nand@83fdb000 {

				compatible = "fsl,imx51-nand";

				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;

				interrupts = <8>;

				clocks = <&clks 60>;

				status = "disabled";

			};



			pata: pata@83fe0000 {

				compatible = "fsl,imx51-pata", "fsl,imx27-pata";

				reg = <0x83fe0000 0x4000>;

				interrupts = <70>;

				clocks = <&clks 161>;

				status = "disabled";

			};



			ssi3: ssi@83fe8000 {

				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";

				reg = <0x83fe8000 0x4000>;

				interrupts = <96>;

				clocks = <&clks 50>;

				dmas = <&sdma 46 0 0>,

				       <&sdma 47 0 0>;

				dma-names = "rx", "tx";

				fsl,fifo-depth = <15>;

				fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */

				status = "disabled";

			};



			fec: ethernet@83fec000 {

				compatible = "fsl,imx51-fec", "fsl,imx27-fec";

				reg = <0x83fec000 0x4000>;

				interrupts = <87>;

				clocks = <&clks 42>, <&clks 42>, <&clks 42>;

				clock-names = "ipg", "ahb", "ptp";

				status = "disabled";

			};

		};

	};

};