Commit 35610745 authored by Kalle Valo's avatar Kalle Valo
Browse files
ath.git patches for v5.20. Major changes:

ath11k:

* fix WCN9074 to work again

* revert rfkill support as it was causing problems
parents 42bbf810 5cc8cc44
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+51 −1
Original line number Diff line number Diff line
@@ -140,8 +140,53 @@ ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector)
	return ab->pci.msi.irqs[vector];
}

static inline u32
ath11k_ahb_get_window_start_wcn6750(struct ath11k_base *ab, u32 offset)
{
	u32 window_start = 0;

	/* If offset lies within DP register range, use 1st window */
	if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
		window_start = ATH11K_PCI_WINDOW_START;
	/* If offset lies within CE register range, use 2nd window */
	else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
		 ATH11K_PCI_WINDOW_RANGE_MASK)
		window_start = 2 * ATH11K_PCI_WINDOW_START;

	return window_start;
}

static void
ath11k_ahb_window_write32_wcn6750(struct ath11k_base *ab, u32 offset, u32 value)
{
	u32 window_start;

	/* WCN6750 uses static window based register access*/
	window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);

	iowrite32(value, ab->mem + window_start +
		  (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
}

static u32 ath11k_ahb_window_read32_wcn6750(struct ath11k_base *ab, u32 offset)
{
	u32 window_start;
	u32 val;

	/* WCN6750 uses static window based register access */
	window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);

	val = ioread32(ab->mem + window_start +
		       (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
	return val;
}

static const struct ath11k_pci_ops ath11k_ahb_pci_ops_wcn6750 = {
	.wakeup = NULL,
	.release = NULL,
	.get_msi_irq = ath11k_ahb_get_msi_irq_wcn6750,
	.window_write32 = ath11k_ahb_window_write32_wcn6750,
	.window_read32 = ath11k_ahb_window_read32_wcn6750,
};

static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
@@ -971,11 +1016,16 @@ static int ath11k_ahb_probe(struct platform_device *pdev)
	}

	ab->hif.ops = hif_ops;
	ab->pci.ops = pci_ops;
	ab->pdev = pdev;
	ab->hw_rev = hw_rev;
	platform_set_drvdata(pdev, ab);

	ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
	if (ret) {
		ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
		goto err_core_free;
	}

	ret = ath11k_core_pre_init(ab);
	if (ret)
		goto err_core_free;
+0 −87
Original line number Diff line number Diff line
@@ -54,9 +54,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 11,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074,
		.svc_to_ce_map_len = 21,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.single_pdev_only = false,
		.rxdma1_enable = true,
		.num_rxmda_per_pdev = 1,
@@ -107,8 +104,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = true,
		.static_window_map = false,
		.hybrid_bus_type = false,
		.dp_window_idx = 0,
		.ce_window_idx = 0,
		.fixed_fw_mem = false,
		.support_off_channel_tx = false,
	},
@@ -133,9 +128,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 11,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018,
		.svc_to_ce_map_len = 19,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.single_pdev_only = false,
		.rxdma1_enable = true,
		.num_rxmda_per_pdev = 1,
@@ -183,8 +175,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = true,
		.static_window_map = false,
		.hybrid_bus_type = false,
		.dp_window_idx = 0,
		.ce_window_idx = 0,
		.fixed_fw_mem = false,
		.support_off_channel_tx = false,
	},
@@ -209,9 +199,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 9,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
		.svc_to_ce_map_len = 14,
		.rfkill_pin = 48,
		.rfkill_cfg = 0,
		.rfkill_on_level = 1,
		.single_pdev_only = true,
		.rxdma1_enable = false,
		.num_rxmda_per_pdev = 2,
@@ -258,8 +245,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = false,
		.static_window_map = false,
		.hybrid_bus_type = false,
		.dp_window_idx = 0,
		.ce_window_idx = 0,
		.fixed_fw_mem = false,
		.support_off_channel_tx = true,
	},
@@ -284,9 +269,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 9,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qcn9074,
		.svc_to_ce_map_len = 18,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.rxdma1_enable = true,
		.num_rxmda_per_pdev = 1,
		.rx_mac_buf_ring = false,
@@ -333,8 +315,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = false,
		.static_window_map = true,
		.hybrid_bus_type = false,
		.dp_window_idx = 3,
		.ce_window_idx = 2,
		.fixed_fw_mem = false,
		.support_off_channel_tx = false,
	},
@@ -359,9 +339,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 9,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
		.svc_to_ce_map_len = 14,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.single_pdev_only = true,
		.rxdma1_enable = false,
		.num_rxmda_per_pdev = 2,
@@ -408,8 +385,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = false,
		.static_window_map = false,
		.hybrid_bus_type = false,
		.dp_window_idx = 0,
		.ce_window_idx = 0,
		.fixed_fw_mem = false,
		.support_off_channel_tx = true,
	},
@@ -434,9 +409,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 9,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
		.svc_to_ce_map_len = 14,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.single_pdev_only = true,
		.rxdma1_enable = false,
		.num_rxmda_per_pdev = 2,
@@ -482,8 +454,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = false,
		.static_window_map = false,
		.hybrid_bus_type = false,
		.dp_window_idx = 0,
		.ce_window_idx = 0,
		.fixed_fw_mem = false,
		.support_off_channel_tx = true,
	},
@@ -508,9 +478,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.target_ce_count = 9,
		.svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_qca6390,
		.svc_to_ce_map_len = 14,
		.rfkill_pin = 0,
		.rfkill_cfg = 0,
		.rfkill_on_level = 0,
		.single_pdev_only = true,
		.rxdma1_enable = false,
		.num_rxmda_per_pdev = 1,
@@ -556,8 +523,6 @@ static const struct ath11k_hw_params ath11k_hw_params[] = {
		.fixed_mem_region = false,
		.static_window_map = true,
		.hybrid_bus_type = true,
		.dp_window_idx = 1,
		.ce_window_idx = 2,
		.fixed_fw_mem = true,
		.support_off_channel_tx = false,
	},
@@ -1402,27 +1367,6 @@ static int ath11k_core_start_firmware(struct ath11k_base *ab,
	return ret;
}

static int ath11k_core_rfkill_config(struct ath11k_base *ab)
{
	struct ath11k *ar;
	int ret = 0, i;

	if (!(ab->target_caps.sys_cap_info & WMI_SYS_CAP_INFO_RFKILL))
		return 0;

	for (i = 0; i < ab->num_radios; i++) {
		ar = ab->pdevs[i].ar;

		ret = ath11k_mac_rfkill_config(ar);
		if (ret && ret != -EOPNOTSUPP) {
			ath11k_warn(ab, "failed to configure rfkill: %d", ret);
			return ret;
		}
	}

	return ret;
}

int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
{
	int ret;
@@ -1475,13 +1419,6 @@ int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab)
		goto err_core_stop;
	}
	ath11k_hif_irq_enable(ab);

	ret = ath11k_core_rfkill_config(ab);
	if (ret && ret != -EOPNOTSUPP) {
		ath11k_err(ab, "failed to config rfkill: %d\n", ret);
		goto err_core_stop;
	}

	mutex_unlock(&ab->core_lock);

	return 0;
@@ -1550,7 +1487,6 @@ void ath11k_core_halt(struct ath11k *ar)
	cancel_delayed_work_sync(&ar->scan.timeout);
	cancel_work_sync(&ar->regd_update_work);
	cancel_work_sync(&ab->update_11d_work);
	cancel_work_sync(&ab->rfkill_work);

	rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL);
	synchronize_rcu();
@@ -1558,28 +1494,6 @@ void ath11k_core_halt(struct ath11k *ar)
	idr_init(&ar->txmgmt_idr);
}

static void ath11k_rfkill_work(struct work_struct *work)
{
	struct ath11k_base *ab = container_of(work, struct ath11k_base, rfkill_work);
	struct ath11k *ar;
	bool rfkill_radio_on;
	int i;

	spin_lock_bh(&ab->base_lock);
	rfkill_radio_on = ab->rfkill_radio_on;
	spin_unlock_bh(&ab->base_lock);

	for (i = 0; i < ab->num_radios; i++) {
		ar = ab->pdevs[i].ar;
		if (!ar)
			continue;

		/* notify cfg80211 radio state change */
		ath11k_mac_rfkill_enable_radio(ar, rfkill_radio_on);
		wiphy_rfkill_set_hw_state(ar->hw->wiphy, !rfkill_radio_on);
	}
}

static void ath11k_update_11d(struct work_struct *work)
{
	struct ath11k_base *ab = container_of(work, struct ath11k_base, update_11d_work);
@@ -1891,7 +1805,6 @@ struct ath11k_base *ath11k_core_alloc(struct device *dev, size_t priv_size,
	init_waitqueue_head(&ab->qmi.cold_boot_waitq);
	INIT_WORK(&ab->restart_work, ath11k_core_restart);
	INIT_WORK(&ab->update_11d_work, ath11k_update_11d);
	INIT_WORK(&ab->rfkill_work, ath11k_rfkill_work);
	INIT_WORK(&ab->reset_work, ath11k_core_reset);
	timer_setup(&ab->rx_replenish_retry, ath11k_ce_rx_replenish_retry, 0);
	init_completion(&ab->htc_suspend);
+0 −4
Original line number Diff line number Diff line
@@ -929,10 +929,6 @@ struct ath11k_base {

	struct ath11k_dbring_cap *db_caps;
	u32 num_db_cap;
	struct work_struct rfkill_work;

	/* true means radio is on */
	bool rfkill_radio_on;

	/* To synchronize 11d scan vdev id */
	struct mutex vdev_id_11d_lock;
+0 −5
Original line number Diff line number Diff line
@@ -153,9 +153,6 @@ struct ath11k_hw_params {
	u32 svc_to_ce_map_len;

	bool single_pdev_only;
	u32 rfkill_pin;
	u32 rfkill_cfg;
	u32 rfkill_on_level;

	bool rxdma1_enable;
	int num_rxmda_per_pdev;
@@ -201,8 +198,6 @@ struct ath11k_hw_params {
	bool fixed_mem_region;
	bool static_window_map;
	bool hybrid_bus_type;
	u8 dp_window_idx;
	u8 ce_window_idx;
	bool fixed_fw_mem;
	bool support_off_channel_tx;
};
+0 −58
Original line number Diff line number Diff line
@@ -5611,63 +5611,6 @@ static int ath11k_mac_mgmt_tx(struct ath11k *ar, struct sk_buff *skb,
	return 0;
}

int ath11k_mac_rfkill_config(struct ath11k *ar)
{
	struct ath11k_base *ab = ar->ab;
	u32 param;
	int ret;

	if (ab->hw_params.rfkill_pin == 0)
		return -EOPNOTSUPP;

	ath11k_dbg(ab, ATH11K_DBG_MAC,
		   "mac rfkill_pin %d rfkill_cfg %d rfkill_on_level %d",
		   ab->hw_params.rfkill_pin, ab->hw_params.rfkill_cfg,
		   ab->hw_params.rfkill_on_level);

	param = FIELD_PREP(WMI_RFKILL_CFG_RADIO_LEVEL,
			   ab->hw_params.rfkill_on_level) |
		FIELD_PREP(WMI_RFKILL_CFG_GPIO_PIN_NUM,
			   ab->hw_params.rfkill_pin) |
		FIELD_PREP(WMI_RFKILL_CFG_PIN_AS_GPIO,
			   ab->hw_params.rfkill_cfg);

	ret = ath11k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_HW_RFKILL_CONFIG,
					param, ar->pdev->pdev_id);
	if (ret) {
		ath11k_warn(ab,
			    "failed to set rfkill config 0x%x: %d\n",
			    param, ret);
		return ret;
	}

	return 0;
}

int ath11k_mac_rfkill_enable_radio(struct ath11k *ar, bool enable)
{
	enum wmi_rfkill_enable_radio param;
	int ret;

	if (enable)
		param = WMI_RFKILL_ENABLE_RADIO_ON;
	else
		param = WMI_RFKILL_ENABLE_RADIO_OFF;

	ath11k_dbg(ar->ab, ATH11K_DBG_MAC, "mac %d rfkill enable %d",
		   ar->pdev_idx, param);

	ret = ath11k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_RFKILL_ENABLE,
					param, ar->pdev->pdev_id);
	if (ret) {
		ath11k_warn(ar->ab, "failed to set rfkill enable param %d: %d\n",
			    param, ret);
		return ret;
	}

	return 0;
}

static void ath11k_mac_op_tx(struct ieee80211_hw *hw,
			     struct ieee80211_tx_control *control,
			     struct sk_buff *skb)
@@ -5922,7 +5865,6 @@ static void ath11k_mac_op_stop(struct ieee80211_hw *hw)
	cancel_delayed_work_sync(&ar->scan.timeout);
	cancel_work_sync(&ar->regd_update_work);
	cancel_work_sync(&ar->ab->update_11d_work);
	cancel_work_sync(&ar->ab->rfkill_work);

	if (ar->state_11d == ATH11K_11D_PREPARING) {
		ar->state_11d = ATH11K_11D_IDLE;
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