Unverified Commit 352dd4e8 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!4630 Add support for Hygon model 6h L3 PMU 

Merge Pull Request from: @hygoner 
 
Add L3 PMU support for Hygon family 18h model 6h processor.

Only Hygon will use family 18h, so minimize the modification and share most
existed codes, see reference [2].

Reference:
[1] https://gitee.com/openeuler/kernel/pulls/1638
[2] https://lkml.iu.edu/hypermail/linux/kernel/1809.2/00921.html 
 
Link:https://gitee.com/openeuler/kernel/pulls/4630

 

Reviewed-by: default avatarXu Kuohai <xukuohai@huawei.com>
Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarWei Li <liwei391@huawei.com>
Signed-off-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
parents 9d9b3971 36a11dc5

arch/x86/events/amd/uncore.c

+27 −2
Original line number Diff line number Diff line
@@ -189,10 +189,21 @@ static void amd_uncore_del(struct perf_event *event, int flags) 
 */

static u64 l3_thread_slice_mask(u64 config)

{

	if (boot_cpu_data.x86 <= 0x18)

	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&

	    boot_cpu_data.x86 <= 0x18)

		return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |

		       ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);



	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

	    boot_cpu_data.x86 == 0x18) {

		if (boot_cpu_data.x86_model == 0x6)

			return ((config & HYGON_L3_SLICE_MASK) ? : HYGON_L3_SLICE_MASK) |

			       ((config & HYGON_L3_THREAD_MASK) ? : HYGON_L3_THREAD_MASK);

		else

			return ((config & AMD64_L3_SLICE_MASK) ? : AMD64_L3_SLICE_MASK) |

			       ((config & AMD64_L3_THREAD_MASK) ? : AMD64_L3_THREAD_MASK);

	}



	/*

	 * If the user doesn't specify a threadmask, they're not trying to

	 * count core 0, so we enable all cores & threads.
@@ -307,6 +318,8 @@ DEFINE_UNCORE_FORMAT_ATTR(threadmask2, threadmask, "config:56-57"); /* F19h L 
DEFINE_UNCORE_FORMAT_ATTR(enallslices,	enallslices,	"config:46");		   /* F19h L3 */

DEFINE_UNCORE_FORMAT_ATTR(enallcores,	enallcores,	"config:47");		   /* F19h L3 */

DEFINE_UNCORE_FORMAT_ATTR(sliceid,	sliceid,	"config:48-50");	   /* F19h L3 */

DEFINE_UNCORE_FORMAT_ATTR(slicemask4,	slicemask,	"config:28-31");	   /* F18h L3 */

DEFINE_UNCORE_FORMAT_ATTR(threadmask32,	threadmask,	"config:32-63");	   /* F18h L3 */



static struct attribute *amd_uncore_df_format_attr[] = {

	&format_attr_event12.attr, /* event14 if F17h+ */
@@ -619,11 +632,23 @@ static int __init amd_uncore_init(void) 
			*l3_attr++ = &format_attr_enallcores.attr;

			*l3_attr++ = &format_attr_sliceid.attr;

			*l3_attr++ = &format_attr_threadmask2.attr;

		} else if (boot_cpu_data.x86 >= 0x17) {

		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&

			   boot_cpu_data.x86 >= 0x17) {

			*l3_attr++ = &format_attr_event8.attr;

			*l3_attr++ = &format_attr_umask.attr;

			*l3_attr++ = &format_attr_slicemask.attr;

			*l3_attr++ = &format_attr_threadmask8.attr;

		} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

			   boot_cpu_data.x86 == 0x18) {

			*l3_attr++ = &format_attr_event8.attr;

			*l3_attr++ = &format_attr_umask.attr;

			if (boot_cpu_data.x86_model == 6) {

				*l3_attr++ = &format_attr_slicemask4.attr;

				*l3_attr++ = &format_attr_threadmask32.attr;

			} else {

				*l3_attr++ = &format_attr_slicemask.attr;

				*l3_attr++ = &format_attr_threadmask8.attr;

			}

		}



		amd_uncore_llc = alloc_percpu(struct amd_uncore *);

arch/x86/include/asm/perf_event.h

+8 −0
Original line number Diff line number Diff line
@@ -48,6 +48,14 @@ 
#define INTEL_ARCH_EVENT_MASK	\

	(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)



#define HYGON_L3_SLICE_SHIFT				28

#define HYGON_L3_SLICE_MASK				\

	(0xFULL << HYGON_L3_SLICE_SHIFT)



#define HYGON_L3_THREAD_SHIFT				32

#define HYGON_L3_THREAD_MASK				\

	(0xFFFFFFFFULL << HYGON_L3_THREAD_SHIFT)



#define AMD64_L3_SLICE_SHIFT				48

#define AMD64_L3_SLICE_MASK				\

	(0xFULL << AMD64_L3_SLICE_SHIFT)