Commit 352938a3 authored by Kunkun Jiang's avatar Kunkun Jiang Committed by Jia Qingtong
Browse files

iommu/arm-smmu-v3: Enable HTTU for stage1 with io-pgtable mapping 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8UZSP


CVE: NA

------------------------------

As nested mode is not upstreamed now, we just aim to support dirty
log tracking for stage1 with io-pgtable mapping (means not support
SVA mapping). If HTTU is supported, we enable HA/HD bits in the SMMU
CD and transfer ARM_HD quirk to io-pgtable.

Signed-off-by: default avatarKeqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarKunkun Jiang <jiangkunkun@huawei.com>
Signed-off-by: default avatarjiaqingtong <jiaqingtong@huawei.com>
parent 3d1d988d

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+4 −0
Original line number Diff line number Diff line
@@ -2184,6 +2184,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, 
			  FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) |

			  FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) |

			  FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) |

			  CTXDESC_CD_0_TCR_HA | CTXDESC_CD_0_TCR_HD |

			  CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64;

	cfg->cd.mair	= pgtbl_cfg->arm_lpae_s1_cfg.mair;
@@ -2289,6 +2290,9 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, 
		.iommu_dev	= smmu->dev,

	};



	if (smmu->features & ARM_SMMU_FEAT_HD)

		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD;



	pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);

	if (!pgtbl_ops)

		return -ENOMEM;