Commit 34eaf30f authored by Nirmoy Das's avatar Nirmoy Das Committed by Alex Deucher
Browse files

drm/amdgpu: detach ring priority from gfx priority 



Currently AMDGPU_RING_PRIO_MAX is redefinition of a
max gfx hwip priority, this won't work well when we will
have a hwip with different set of priorities than gfx.
Also, HW ring priorities are different from ring priorities.

Create a global enum for ring priority levels which each
HWIP can use to define its own priority levels.

Signed-off-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 84d588c3

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+1 −1
Original line number Diff line number Diff line
@@ -109,7 +109,7 @@ static int amdgpu_ctx_priority_permit(struct drm_file *filp, 
	return -EACCES;

}



static enum gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio)

static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_compute_prio(int32_t prio)

{

	switch (prio) {

	case AMDGPU_CTX_PRIORITY_HIGH:

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

+3 −4
Original line number Diff line number Diff line
@@ -42,10 +42,9 @@ 
#define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES

#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES



enum gfx_pipe_priority {

	AMDGPU_GFX_PIPE_PRIO_NORMAL = 1,

	AMDGPU_GFX_PIPE_PRIO_HIGH,

	AMDGPU_GFX_PIPE_PRIO_MAX

enum amdgpu_gfx_pipe_priority {

	AMDGPU_GFX_PIPE_PRIO_NORMAL = AMDGPU_RING_PRIO_1,

	AMDGPU_GFX_PIPE_PRIO_HIGH = AMDGPU_RING_PRIO_2

};



/* Argument for PPSMC_MSG_GpuChangeState */

drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h

+7 −2
Original line number Diff line number Diff line
@@ -36,8 +36,13 @@ 
#define AMDGPU_MAX_VCE_RINGS		3

#define AMDGPU_MAX_UVD_ENC_RINGS	2



#define AMDGPU_RING_PRIO_DEFAULT	1

#define AMDGPU_RING_PRIO_MAX		AMDGPU_GFX_PIPE_PRIO_MAX

enum amdgpu_ring_priority_level {

	AMDGPU_RING_PRIO_0,

	AMDGPU_RING_PRIO_1,

	AMDGPU_RING_PRIO_DEFAULT = 1,

	AMDGPU_RING_PRIO_2,

	AMDGPU_RING_PRIO_MAX

};



/* some special values for the owner field */

#define AMDGPU_FENCE_OWNER_UNDEFINED	((void *)0ul)