Commit 34dd3ccc authored by Ben Chuang's avatar Ben Chuang Committed by Ulf Hansson
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mmc: sdhci-pci-gli: Fine tune GL9763E L1 entry delay 



Fine tune the value to 21us in order to improve read/write performance.

Signed-off-by: default avatarBen Chuang <benchuanggli@gmail.com>
Link: https://lore.kernel.org/r/20210511061835.5559-1-benchuanggli@gmail.com


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 110a8688

drivers/mmc/host/sdhci-pci-gli.c

+2 −2
Original line number Diff line number Diff line
@@ -94,7 +94,7 @@ 


#define PCIE_GLI_9763E_CFG2      0x8A4

#define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)

#define   GLI_9763E_CFG2_L1DLY_MID 0x50

#define   GLI_9763E_CFG2_L1DLY_MID 0x54



#define PCIE_GLI_9763E_MMC_CTRL  0x960

#define   GLI_9763E_HS400_SLOW     BIT(3)
@@ -847,7 +847,7 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 


	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);

	value &= ~GLI_9763E_CFG2_L1DLY;

	/* set ASPM L1 entry delay to 20us */

	/* set ASPM L1 entry delay to 21us */

	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);

	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);