Unverified Commit 34827ffe authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ixp4xx-dts-arm-soc-v5.15-1' of... 

Merge tag 'ixp4xx-dts-arm-soc-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt

IXP4xx DTS file updates for the v5.15 kernel cycle:

- Fix up some (non-urgent) IRQ flags for the PCI buses.

- Add the second UART to the generic ixp4xx.dtsi

- Make use of the new expansion bus driver in all device
  trees with e.g. flash memory on the expansion bus.

- Adds the CF card slot to the Gateworks GW2358.

- Add new device trees for:
  - Iomega NAS 100D
  - D-Link DSM-G600
  - Netgear WG302v2
  - Arcom Vulcan
  - Gateworks Avila GW2348
  - Intel IXPD425 and siblings
  - Coyote and IXDPG425
  - Linksys WRV54G

* tag 'ixp4xx-dts-arm-soc-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
  ARM: dts: ixp4xx: Add a devicetree for Freecom FSG-3
  ARM: dts: ixp4xx: Add devicetree for Linksys WRV54G
  ARM: dts: ixp4xx: Add device trees for Coyote and IXDPG425
  ARM: dts: ixp4xx: Add Intel IXDP425 etc reference designs
  ARM: dts: ixp4xx: Add CF to GW2358
  ARM: dts: ixp4xx: Add Gateworks Avila GW2348 device tree
  ARM: dts: ixp4xx: Add Arcom Vulcan device tree
  ARM: dts: ixp4xx: Add devicetree for Netgear WG302v2
  ARM: dts: ixp4xx: Use the expansion bus
  ARM: dts: ixp4xx: Add second UART
  ARM: dts: ixp4xx: Add devicetree for D-Link DSM-G600 rev A
  ARM: dts: ixp4xx: Move EPBX100 flash to external bus node
  ARM: dts: ixp4xx: Add devicetree for Iomega NAS 100D
  ARM: dts: ixp4xx: Fix up bad interrupt flags

Link: https://lore.kernel.org/r/CACRpkdY19AvWT--OcmEKbwFue_EcThVs7uZeHkzORten7xj-RA@mail.gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 57798ff2 f2841e3a

arch/arm/boot/dts/Makefile

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@@ -243,8 +243,20 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ 
	integratorcp.dtb

dtb-$(CONFIG_ARCH_IXP4XX) += \

	intel-ixp42x-linksys-nslu2.dtb \

	intel-ixp42x-linksys-wrv54g.dtb \

	intel-ixp42x-freecom-fsg-3.dtb \

	intel-ixp42x-welltech-epbx100.dtb \

	intel-ixp43x-gateworks-gw2358.dtb

	intel-ixp42x-ixdp425.dtb \

	intel-ixp43x-kixrp435.dtb \

	intel-ixp46x-ixdp465.dtb \

	intel-ixp42x-adi-coyote.dtb \

	intel-ixp42x-ixdpg425.dtb \

	intel-ixp42x-iomega-nas100d.dtb \

	intel-ixp42x-dlink-dsm-g600.dtb \

	intel-ixp42x-gateworks-gw2348.dtb \

	intel-ixp43x-gateworks-gw2358.dtb \

	intel-ixp42x-netgear-wg302v2.dtb \

	intel-ixp42x-arcom-vulcan.dtb

dtb-$(CONFIG_ARCH_KEYSTONE) += \

	keystone-k2hk-evm.dtb \

	keystone-k2l-evm.dtb \

arch/arm/boot/dts/intel-ixp42x-adi-coyote.dts

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// SPDX-License-Identifier: ISC

/*

 * Device Tree file for ADI Engineering Coyote platform.

 * Derived from boardfiles written by MontaVista software.

 * Ethernet set-up from OpenWrt.

 */



/dts-v1/;



#include "intel-ixp42x.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "ADI Engineering Coyote reference design";

	compatible = "adieng,coyote", "intel,ixp42x";

	#address-cells = <1>;

	#size-cells = <1>;



	memory@0 {

		/* CHECKME: 16 MB SDRAM minimum, maybe the Coyote actually has more */

		device_type = "memory";

		reg = <0x00000000 0x01000000>;

	};



	chosen {

		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";

		stdout-path = "uart1:115200n8";

	};



	aliases {

		/* These are switched around */

		serial0 = &uart1;

		serial1 = &uart0;

	};



	soc {

		bus@c4000000 {

			flash@0,0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 32 MB of Flash in 128 0x20000 sized blocks

				 * mapped in at CS0 and CS1

				 */

				reg = <0 0x00000000 0x2000000>;



				/* Configure expansion bus to allow writes */

				intel,ixp4xx-eb-write-enable = <1>;



				partitions {

					compatible = "redboot-fis";

					/* CHECKME: guess this is Redboot FIS */

					fis-index-block = <0x1ff>;

				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Taken from Coyote PCI boardfile.

			 * We have slots (IDSEL) 1 and 2 with one assigned IRQ

			 * each handling all IRQs.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 6 */

			<0x0800 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 6 */

			<0x0800 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 6 */

			<0x0800 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 6 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */

			<0x1000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 11 */

			<0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */

			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 11 */

		};



		/* EthB */

		ethernet@c8009000 {

			status = "ok";

			queue-rx = <&qmgr 3>;

			queue-txready = <&qmgr 20>;

			phy-mode = "rgmii";

			phy-handle = <&phy5>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy4: ethernet-phy@4 {

					reg = <4>;

				};



				phy5: ethernet-phy@5 {

					reg = <5>;

				};

			};

		};



		/* EthC */

		ethernet@c800a000 {

			status = "ok";

			queue-rx = <&qmgr 4>;

			queue-txready = <&qmgr 21>;

			phy-mode = "rgmii";

			phy-handle = <&phy4>;

		};

	};

};

arch/arm/boot/dts/intel-ixp42x-arcom-vulcan.dts

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// SPDX-License-Identifier: ISC

/*

 * Device Tree file for the Arcom/Eurotech Vulcan board.

 * This board is a single board computer in the PC/104 form factor based on

 * IXP425, and was released around 2005. It previously had the name "Mercury".

 */



/dts-v1/;



#include "intel-ixp42x.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "Arcom/Eurotech Vulcan";

	compatible = "arcom,vulcan", "intel,ixp42x";

	#address-cells = <1>;

	#size-cells = <1>;



	memory@0 {

		device_type = "memory";

		reg = <0x00000000 0x4000000>;

	};



	chosen {

		/* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */

		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";

		stdout-path = "uart0:115200n8";

	};



	aliases {

		serial0 = &uart0;

	};



	onewire {

		compatible = "w1-gpio";

		gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

	};



	soc {

		bus@c4000000 {

			flash@0,0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 32 MB of Flash in 0x20000 byte blocks

				 * mapped in at CS0 and CS1.

				 *

				 * The documentation mentions the existence

				 * of a 16MB version, which we conveniently

				 * ignore. Shout if you own one!

				 */

				reg = <0 0x00000000 0x2000000>;



				/* Expansion bus settings */

				intel,ixp4xx-eb-t3 = <3>;

				intel,ixp4xx-eb-byte-access-on-halfword = <1>;

				intel,ixp4xx-eb-write-enable = <1>;



				partitions {

					compatible = "redboot-fis";

					fis-index-block = <0x1ff>;

				};

			};

			sram@2,0 {

				/* 256 KB SDRAM memory at CS2 */

				compatible = "shared-dma-pool";

				device_type = "memory";

				reg = <2 0x00000000 0x40000>;

				no-map;

				/* Expansion bus settings */

				intel,ixp4xx-eb-t3 = <1>;

				intel,ixp4xx-eb-t4 = <2>;

				intel,ixp4xx-eb-ahb-split-transfers = <1>;

				intel,ixp4xx-eb-write-enable = <1>;

				intel,ixp4xx-eb-byte-access = <1>;

			};

			serial@3,0 {

				/*

				 * 8250-compatible Exar XR16L2551 2 x UART

				 *

				 * CHECKME: if special tweaks are needed, then fix the

				 * operating system to handle it.

				 */

				compatible = "exar,xr16l2551", "ns8250";

				reg = <3 0x00000000 0x10>;

				interrupt-parent = <&gpio0>;

				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;

				clock-frequency = <1843200>;

				/* Expansion bus settings */

				intel,ixp4xx-eb-t3 = <3>;

				intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */

				intel,ixp4xx-eb-write-enable = <1>;

				intel,ixp4xx-eb-byte-access = <1>;

			};

			gpio1: gpio@4,0 {

				/*

				 * MMIO GPIO in one byte

				 */

				compatible = "arcom,vulcan-gpio";

				reg = <4 0x00000000 0x1>;

				/* Expansion bus settings */

				intel,ixp4xx-eb-write-enable = <1>;

				intel,ixp4xx-eb-byte-access = <1>;

			};

			watchdog@5,0 {

				compatible = "maxim,max6369";

				reg = <5 0x00000000 0x1>;

				/* Expansion bus settings */

				intel,ixp4xx-eb-write-enable = <1>;

				intel,ixp4xx-eb-byte-access = <1>;

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Taken from Vulcan PCI boardfile.

			 *

			 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt

			 * per slot. This interrupt is shared (OR:ed) by all four pins.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */

			<0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */

			<0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */

			<0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */

			<0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */

			<0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */

			<0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */

		};



		/* EthB */

		ethernet@c8009000 {

			status = "ok";

			queue-rx = <&qmgr 3>;

			queue-txready = <&qmgr 20>;

			phy-mode = "rgmii";

			phy-handle = <&phy0>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy0: ethernet-phy@0 {

					reg = <0>;

				};



				phy1: ethernet-phy@1 {

					reg = <1>;

				};

			};

		};



		/* EthC */

		ethernet@c800a000 {

			status = "ok";

			queue-rx = <&qmgr 4>;

			queue-txready = <&qmgr 21>;

			phy-mode = "rgmii";

			phy-handle = <&phy1>;

		};

	};

};

arch/arm/boot/dts/intel-ixp42x-dlink-dsm-g600.dts

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// SPDX-License-Identifier: ISC

/*

 * Device Tree file for D-Link DSM-G600 revision A based on IXP420

 * NOTE: revision B of this device uses PowerPC and is NOT supported by

 * this device tree.

 *

 * Inspired by the boardfile by Rod Whitby, Tower Technologies, Alessandro Zummo

 * and Michael Westerhof.

 */



/dts-v1/;



#include "intel-ixp42x.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "D-Link DSM-G600 rev A";

	compatible = "dlink,dsm-g600-a", "intel,ixp42x";

	#address-cells = <1>;

	#size-cells = <1>;



	memory@0 {

		/* 64 MB SDRAM */

		device_type = "memory";

		reg = <0x00000000 0x4000000>;

	};



	chosen {

		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";

		stdout-path = "uart0:115200n8";

	};



	aliases {

		serial0 = &uart0;

	};



	leds {

		compatible = "gpio-leds";

		led-power {

			label = "dsmg600:green:power";

			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;

			default-state = "on";

			linux,default-trigger = "heartbeat";

		};

		led-wlan {

			label = "dsmg600:green:wlan";

			/* CHECKME: flagged as active low in the old board file */

			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;

			default-state = "on";

			/* We don't have WLAN trigger in the kernel (yet) */

			linux,default-trigger = "netdev";

		};

	};



	gpio_keys {

		compatible = "gpio-keys";



		button-reset {

			wakeup-source;

			linux,code = <KEY_ESC>;

			label = "reset";

			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;

		};

	};



	gpio_keys_polled {

		compatible = "gpio-keys-polled";



		/*

		 * According to the board file this key cannot handle interrupts and

		 * need to be polled. Investigate if this is really the case or if

		 * this can be moved adjacent to the ordinary gpio-keys above.

		 */

		button-power {

			wakeup-source;

			linux,code = <KEY_POWER>;

			label = "power";

			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;

		};

	};



	i2c {

		compatible = "i2c-gpio";

		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

		scl-gpios = <&gpio0 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

		#address-cells = <1>;

		#size-cells = <0>;



		rtc@51 {

			compatible = "nxp,pcf8563";

			reg = <0x51>;

		};

	};



	gpio-poweroff {

		compatible = "gpio-poweroff";

		gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;

		timeout-ms = <5000>;

	};



	soc {

		bus@c4000000 {

			/* The first 16MB region at CS0 on the expansion bus */

			flash@0,0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/*

				 * 16 MB of Flash in 128 0x20000 sized blocks

				 * mapped in at CS0.

				 */

				reg = <0 0x00000000 0x1000000>;



				partitions {

					compatible = "redboot-fis";

					/*

					 * A boot log says the directory is at 0xfe0000

					 * 0x7f * 0x20000 = 0xfe0000

					 */

					fis-index-block = <0x7f>;

				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Taken from DSM-G600 PCI boardfile (dsmg600-pci.c)

			 * We have slots (IDSEL) 1, 2, 3, 4 and pins 1, 2 and 3.

			 * Only slot 3 have three IRQs.

			 */

			interrupt-map =

			/* IDSEL 1 */

			<0x0800 0 0 1 &gpio0 7  IRQ_TYPE_LEVEL_LOW>, /* INT E on slot 1 is irq 7 */

			/* IDSEL 2 */

			<0x1000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 11 */

			/* IDSEL 3 */

			<0x1800 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 10 */

			<0x1800 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 9 */

			<0x1800 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 8 */

			/* IDSEL 4 */

			<0x2000 0 0 3 &gpio0 6  IRQ_TYPE_LEVEL_LOW>; /* INT F on slot 4 is irq 6 */

		};

	};

};

arch/arm/boot/dts/intel-ixp42x-freecom-fsg-3.dts

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// SPDX-License-Identifier: ISC

/*

 * Device Tree file for the Freecom FSG-3 router.

 * This machine is based on IXP425.

 * This device tree is inspired by the board file by Rod Whitby.

 */



/dts-v1/;



#include "intel-ixp42x.dtsi"

#include <dt-bindings/input/input.h>



/ {

	model = "Freecom FSG-3";

	compatible = "freecom,fsg-3", "intel,ixp42x";

	#address-cells = <1>;

	#size-cells = <1>;



	memory@0 {

		/* 64 MB memory */

		device_type = "memory";

		reg = <0x00000000 0x4000000>;

	};



	chosen {

		/* Boot from the first partition on the hard drive */

		bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait";

		stdout-path = "uart0:115200n8";

	};



	aliases {

		serial0 = &uart0;

	};



	gpio_keys {

		compatible = "gpio-keys";



		button-sync {

			wakeup-source;

			/* Closest approximation of what the key should do */

			linux,code = <KEY_CONNECT>;

			label = "sync";

			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;

		};

		button-reset {

			wakeup-source;

			linux,code = <KEY_ESC>;

			label = "reset";

			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;

		};

		button-usb {

			wakeup-source;

			/* Unplug USB, closest approximation of what the key should do */

			linux,code = <KEY_EJECTCD>;

			label = "usb";

			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;

		};

	};



	i2c {

		compatible = "i2c-gpio";

		sda-gpios = <&gpio0 12 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

		scl-gpios = <&gpio0 13 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;

		#address-cells = <1>;

		#size-cells = <0>;



		hwmon@28 {

			/*

			 * Temperature sensor and fan control chip.

			 *

			 * TODO: create a proper device tree binding for

			 * the sensor and temperature zone and create a

			 * zone with fan control.

			 */

			compatible = "winbond,w83781d";

			reg = <0x28>;

		};

		rtc@6f {

			compatible = "isil,isl1208";

			reg = <0x6f>;

		};

	};



	soc {

		bus@c4000000 {

			flash@0,0 {

				compatible = "intel,ixp4xx-flash", "cfi-flash";

				bank-width = <2>;

				/* Enable writes on the expansion bus */

				intel,ixp4xx-eb-write-enable = <1>;

				/* 4 MB of Flash mapped in at CS0 */

				reg = <0 0x00000000 0x400000>;



				partitions {

					compatible = "redboot-fis";

					/* Eraseblock at 0x3e0000 */

					fis-index-block = <0x1f>;

				};

			};

		};



		pci@c0000000 {

			status = "ok";



			/*

			 * Written based on the FSG-3 PCI boardfile.

			 * We have slots 12, 13 & 14 (IDSEL) with one IRQ each.

			 */

			interrupt-map =

			/* IDSEL 12 */

			<0x6000 0 0 1 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 5 */

			<0x6000 0 0 2 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 5 */

			<0x6000 0 0 3 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 5 */

			<0x6000 0 0 4 &gpio0 5 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 5 */

			/* IDSEL 13 */

			<0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */

			<0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */

			<0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */

			<0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */

			/* IDSEL 14 */

			<0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */

			<0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */

			<0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */

			<0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */

		};



		/* EthB */

		ethernet@c8009000 {

			status = "ok";

			queue-rx = <&qmgr 3>;

			queue-txready = <&qmgr 20>;

			phy-mode = "rgmii";

			phy-handle = <&phy5>;



			mdio {

				#address-cells = <1>;

				#size-cells = <0>;



				phy4: ethernet-phy@4 {

					reg = <4>;

				};



				phy5: ethernet-phy@5 {

					reg = <5>;

				};

			};

		};



		/* EthC */

		ethernet@c800a000 {

			status = "ok";

			queue-rx = <&qmgr 4>;

			queue-txready = <&qmgr 21>;

			phy-mode = "rgmii";

			phy-handle = <&phy4>;

		};

	};

};