Commit 3478f90c authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'crypto-chelsio-Restructure-chelsio-s-inline-crypto-drivers' 



Vinay Kumar Yadav says:

====================
crypto/chelsio: Restructure chelsio's inline crypto drivers

This series of patches will move chelsio's inline crypto
drivers (ipsec and chtls) from "drivers/crypto/chelsio/"
to "drivers/net/ethernet/chelsio/inline_crypto/"
for better maintenance.

Patch1: moves out chtls.
Patch2: moves out inline ipsec, applies on top of Patch1.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d0a84e1f 1b77be46

MAINTAINERS

+9 −0
Original line number Diff line number Diff line
@@ -4692,6 +4692,15 @@ S: Supported 
W:	http://www.chelsio.com

F:	drivers/crypto/chelsio









CXGB4 INLINE CRYPTO DRIVER









M:	Ayush Sawal <ayush.sawal@chelsio.com>









M:	Vinay Kumar Yadav <vinay.yadav@chelsio.com>









M:	Rohit Maheshwari <rohitm@chelsio.com>









L:	netdev@vger.kernel.org









S:	Supported









W:	http://www.chelsio.com









F:	drivers/net/ethernet/chelsio/inline_crypto/

















CXGB4 ETHERNET DRIVER (CXGB4)









M:	Vishal Kulkarni <vishal@chelsio.com>









L:	netdev@vger.kernel.org
































drivers/crypto/chelsio/Kconfig



+0
−21






























Original line number
Diff line number
Diff line







@@ -22,27 +22,6 @@ config CRYPTO_DEV_CHELSIO







	  To compile this driver as a module, choose M here: the module









	  will be called chcr.



















config CHELSIO_IPSEC_INLINE









	bool "Chelsio IPSec XFRM Tx crypto offload"









	depends on CHELSIO_T4









	depends on CRYPTO_DEV_CHELSIO









	depends on XFRM_OFFLOAD









	depends on INET_ESP_OFFLOAD || INET6_ESP_OFFLOAD









	default n









	help









	  Enable support for IPSec Tx Inline.



















config CRYPTO_DEV_CHELSIO_TLS









	tristate "Chelsio Crypto Inline TLS Driver"









	depends on CHELSIO_T4









	depends on TLS_TOE









	select CRYPTO_DEV_CHELSIO









	help









	  Support Chelsio Inline TLS with Chelsio crypto accelerator.



















	  To compile this driver as a module, choose M here: the module









	  will be called chtls.



















config CHELSIO_TLS_DEVICE









	bool "Chelsio Inline KTLS Offload"









	depends on CHELSIO_T4
































drivers/crypto/chelsio/Makefile



+0
−2






























Original line number
Diff line number
Diff line







@@ -6,5 +6,3 @@ chcr-objs :=  chcr_core.o chcr_algo.o







#ifdef CONFIG_CHELSIO_TLS_DEVICE









chcr-objs += chcr_ktls.o









#endif








chcr-$(CONFIG_CHELSIO_IPSEC_INLINE) += chcr_ipsec.o









obj-$(CONFIG_CRYPTO_DEV_CHELSIO_TLS) += chtls/
























drivers/crypto/chelsio/chcr_algo.h



+0
−33






























Original line number
Diff line number
Diff line







@@ -86,39 +86,6 @@







	 KEY_CONTEXT_OPAD_PRESENT_M)









#define KEY_CONTEXT_OPAD_PRESENT_F      KEY_CONTEXT_OPAD_PRESENT_V(1U)



















#define TLS_KEYCTX_RXFLIT_CNT_S 24









#define TLS_KEYCTX_RXFLIT_CNT_V(x) ((x) << TLS_KEYCTX_RXFLIT_CNT_S)



















#define TLS_KEYCTX_RXPROT_VER_S 20









#define TLS_KEYCTX_RXPROT_VER_M 0xf









#define TLS_KEYCTX_RXPROT_VER_V(x) ((x) << TLS_KEYCTX_RXPROT_VER_S)



















#define TLS_KEYCTX_RXCIPH_MODE_S 16









#define TLS_KEYCTX_RXCIPH_MODE_M 0xf









#define TLS_KEYCTX_RXCIPH_MODE_V(x) ((x) << TLS_KEYCTX_RXCIPH_MODE_S)



















#define TLS_KEYCTX_RXAUTH_MODE_S 12









#define TLS_KEYCTX_RXAUTH_MODE_M 0xf









#define TLS_KEYCTX_RXAUTH_MODE_V(x) ((x) << TLS_KEYCTX_RXAUTH_MODE_S)



















#define TLS_KEYCTX_RXCIAU_CTRL_S 11









#define TLS_KEYCTX_RXCIAU_CTRL_V(x) ((x) << TLS_KEYCTX_RXCIAU_CTRL_S)



















#define TLS_KEYCTX_RX_SEQCTR_S 9









#define TLS_KEYCTX_RX_SEQCTR_M 0x3









#define TLS_KEYCTX_RX_SEQCTR_V(x) ((x) << TLS_KEYCTX_RX_SEQCTR_S)



















#define TLS_KEYCTX_RX_VALID_S 8









#define TLS_KEYCTX_RX_VALID_V(x) ((x) << TLS_KEYCTX_RX_VALID_S)



















#define TLS_KEYCTX_RXCK_SIZE_S 3









#define TLS_KEYCTX_RXCK_SIZE_M 0x7









#define TLS_KEYCTX_RXCK_SIZE_V(x) ((x) << TLS_KEYCTX_RXCK_SIZE_S)



















#define TLS_KEYCTX_RXMK_SIZE_S 0









#define TLS_KEYCTX_RXMK_SIZE_M 0x7









#define TLS_KEYCTX_RXMK_SIZE_V(x) ((x) << TLS_KEYCTX_RXMK_SIZE_S)



















#define CHCR_HASH_MAX_DIGEST_SIZE 64









#define CHCR_MAX_SHA_DIGEST_SIZE 64










































drivers/crypto/chelsio/chcr_core.c



+2
−40






























Original line number
Diff line number
Diff line







@@ -40,10 +40,6 @@ static const struct tlsdev_ops chcr_ktls_ops = {







};









#endif



















#ifdef CONFIG_CHELSIO_IPSEC_INLINE









static void update_netdev_features(void);









#endif /* CONFIG_CHELSIO_IPSEC_INLINE */



















static chcr_handler_func work_handlers[NUM_CPL_CMDS] = {









	[CPL_FW6_PLD] = cpl_fw6_pld_handler,









#ifdef CONFIG_CHELSIO_TLS_DEVICE








@@ -60,10 +56,8 @@ static struct cxgb4_uld_info chcr_uld_info = {







	.add = chcr_uld_add,









	.state_change = chcr_uld_state_change,









	.rx_handler = chcr_uld_rx_handler,









#if defined(CONFIG_CHELSIO_IPSEC_INLINE) || defined(CONFIG_CHELSIO_TLS_DEVICE)









	.tx_handler = chcr_uld_tx_handler,









#endif /* CONFIG_CHELSIO_IPSEC_INLINE || CONFIG_CHELSIO_TLS_DEVICE */









#if defined(CONFIG_CHELSIO_TLS_DEVICE)









	.tx_handler = chcr_uld_tx_handler,









	.tlsdev_ops = &chcr_ktls_ops,









#endif









};








@@ -241,19 +235,11 @@ int chcr_uld_rx_handler(void *handle, const __be64 *rsp,







	return 0;









}



















#if defined(CONFIG_CHELSIO_IPSEC_INLINE) || defined(CONFIG_CHELSIO_TLS_DEVICE)









#if defined(CONFIG_CHELSIO_TLS_DEVICE)









int chcr_uld_tx_handler(struct sk_buff *skb, struct net_device *dev)









{









	/* In case if skb's decrypted bit is set, it's nic tls packet, else it's









	 * ipsec packet.









	 */









#ifdef CONFIG_CHELSIO_TLS_DEVICE









	if (skb->decrypted)









		return chcr_ktls_xmit(skb, dev);









#endif









#ifdef CONFIG_CHELSIO_IPSEC_INLINE









	return chcr_ipsec_xmit(skb, dev);









#endif









	return 0;









}









#endif /* CONFIG_CHELSIO_IPSEC_INLINE || CONFIG_CHELSIO_TLS_DEVICE */








@@ -305,24 +291,6 @@ static int chcr_uld_state_change(void *handle, enum cxgb4_state state)







	return ret;









}



















#ifdef CONFIG_CHELSIO_IPSEC_INLINE









static void update_netdev_features(void)









{









	struct uld_ctx *u_ctx, *tmp;



















	mutex_lock(&drv_data.drv_mutex);









	list_for_each_entry_safe(u_ctx, tmp, &drv_data.inact_dev, entry) {









		if (u_ctx->lldi.crypto & ULP_CRYPTO_IPSEC_INLINE)









			chcr_add_xfrmops(&u_ctx->lldi);









	}









	list_for_each_entry_safe(u_ctx, tmp, &drv_data.act_dev, entry) {









		if (u_ctx->lldi.crypto & ULP_CRYPTO_IPSEC_INLINE)









			chcr_add_xfrmops(&u_ctx->lldi);









	}









	mutex_unlock(&drv_data.drv_mutex);









}









#endif /* CONFIG_CHELSIO_IPSEC_INLINE */



















static int __init chcr_crypto_init(void)









{









	INIT_LIST_HEAD(&drv_data.act_dev);








@@ -332,12 +300,6 @@ static int __init chcr_crypto_init(void)







	drv_data.last_dev = NULL;









	cxgb4_register_uld(CXGB4_ULD_CRYPTO, &chcr_uld_info);



















	#ifdef CONFIG_CHELSIO_IPSEC_INLINE









	rtnl_lock();









	update_netdev_features();









	rtnl_unlock();









	#endif /* CONFIG_CHELSIO_IPSEC_INLINE */



















	return 0;









}