Commit 345ce3fc authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: add support for three new square pattern variants from DP2.1 specs 



[why]
DP2.1 specs has brought 3 new variants of sqaure patterns with different
pre-shoot and de-emphasis equalization requirements. The commit adds
logic to identify these variants and apply corresponding eqaulization
requirements into hardware lane settings.

Reviewed-by: default avatarGeorge Shen <George.Shen@amd.com>
Acked-by: default avatarJasdeep Dhillon <jdhillon@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 752e89a7

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+39 −9
Original line number Diff line number Diff line
@@ -4094,6 +4094,12 @@ static void dp_test_send_link_training(struct dc_link *link) 
	dp_retrain_link_dp_test(link, &link_settings, false);

}



static bool is_dp_phy_sqaure_pattern(enum dp_test_pattern test_pattern)

{

	return (DP_TEST_PATTERN_SQUARE_BEGIN <= test_pattern &&

			test_pattern <= DP_TEST_PATTERN_SQUARE_END);

}



/* TODO Raven hbr2 compliance eye output is unstable

 * (toggling on and off) with debugger break

 * This caueses intermittent PHY automation failure
@@ -4111,6 +4117,8 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) 
	union lane_adjust dpcd_lane_adjust;

	unsigned int lane;

	struct link_training_settings link_training_settings;

	unsigned char no_preshoot = 0;

	unsigned char no_deemphasis = 0;



	dpcd_test_pattern.raw = 0;

	memset(dpcd_lane_adjustment, 0, sizeof(dpcd_lane_adjustment));
@@ -4204,8 +4212,21 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) 
	case PHY_TEST_PATTERN_264BIT_CUSTOM:

		test_pattern = DP_TEST_PATTERN_264BIT_CUSTOM;

		break;

	case PHY_TEST_PATTERN_SQUARE_PULSE:

		test_pattern = DP_TEST_PATTERN_SQUARE_PULSE;

	case PHY_TEST_PATTERN_SQUARE:

		test_pattern = DP_TEST_PATTERN_SQUARE;

		break;

	case PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:

		test_pattern = DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED;

		no_preshoot = 1;

		break;

	case PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:

		test_pattern = DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED;

		no_deemphasis = 1;

		break;

	case PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:

		test_pattern = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED;

		no_preshoot = 1;

		no_deemphasis = 1;

		break;

	default:

		test_pattern = DP_TEST_PATTERN_VIDEO_MODE;
@@ -4222,7 +4243,7 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) 
				test_pattern_size);

	}



	if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE) {

	if (is_dp_phy_sqaure_pattern(test_pattern)) {

		test_pattern_size = 1; // Square pattern data is 1 byte (DP spec)

		core_link_read_dpcd(

				link,
@@ -4259,8 +4280,10 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) 
				((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03);

		} else if (dp_get_link_encoding_format(&link->cur_link_settings) ==

				DP_128b_132b_ENCODING) {

			link_training_settings.hw_lane_settings[lane].FFE_PRESET.raw =

			link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.level =

					dpcd_lane_adjust.tx_ffe.PRESET_VALUE;

			link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.no_preshoot = no_preshoot;

			link_training_settings.hw_lane_settings[lane].FFE_PRESET.settings.no_deemphasis = no_deemphasis;

		}

	}
@@ -6178,8 +6201,17 @@ bool dc_link_dp_set_test_pattern( 
		case DP_TEST_PATTERN_264BIT_CUSTOM:

			pattern = PHY_TEST_PATTERN_264BIT_CUSTOM;

			break;

		case DP_TEST_PATTERN_SQUARE_PULSE:

			pattern = PHY_TEST_PATTERN_SQUARE_PULSE;

		case DP_TEST_PATTERN_SQUARE:

			pattern = PHY_TEST_PATTERN_SQUARE;

			break;

		case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:

			pattern = PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED;

			break;

		case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:

			pattern = PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED;

			break;

		case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:

			pattern = PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED;

			break;

		default:

			return false;
@@ -6190,14 +6222,12 @@ bool dc_link_dp_set_test_pattern( 
			return false;



		if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {

#if defined(CONFIG_DRM_AMD_DC_DCN)

			if (test_pattern == DP_TEST_PATTERN_SQUARE_PULSE)

			if (is_dp_phy_sqaure_pattern(test_pattern))

				core_link_write_dpcd(link,

						DP_LINK_SQUARE_PATTERN,

						p_custom_pattern,

						1);



#endif

			/* tell receiver that we are sending qualification

			 * pattern DP 1.2 or later - DP receiver's link quality

			 * pattern is set using DPCD LINK_QUAL_LANEx_SET

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+3 −0
Original line number Diff line number Diff line
@@ -925,6 +925,9 @@ struct dpcd_usb4_dp_tunneling_info { 
#ifndef DP_128b_132b_TRAINING_AUX_RD_INTERVAL

#define DP_128b_132b_TRAINING_AUX_RD_INTERVAL		0x2216

#endif

#ifndef DP_LINK_SQUARE_PATTERN

#define DP_LINK_SQUARE_PATTERN				0x10F

#endif

#ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX

#define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPRX		0x2217

#endif

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_link_encoder.c

+4 −1
Original line number Diff line number Diff line
@@ -242,7 +242,10 @@ void dcn31_hpo_dp_link_enc_set_link_test_pattern( 
		REG_UPDATE(DP_DPHY_SYM32_CONTROL,

				MODE, DP2_TEST_PATTERN);

		break;

	case DP_TEST_PATTERN_SQUARE_PULSE:

	case DP_TEST_PATTERN_SQUARE:

	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED:

	case DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED:

	case DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED:

		REG_SET(DP_DPHY_SYM32_TP_SQ_PULSE, 0,

				TP_SQ_PULSE_WIDTH, tp_params->custom_pattern[0]);

drivers/gpu/drm/amd/display/include/dpcd_defs.h

+4 −1
Original line number Diff line number Diff line
@@ -88,7 +88,10 @@ enum dpcd_phy_test_patterns { 
	PHY_TEST_PATTERN_PRBS23 = 0x30,

	PHY_TEST_PATTERN_PRBS31 = 0x38,

	PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,

	PHY_TEST_PATTERN_SQUARE_PULSE = 0x48,

	PHY_TEST_PATTERN_SQUARE = 0x48,

	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,

	PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,

	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,

};



enum dpcd_test_dyn_range {

drivers/gpu/drm/amd/display/include/link_service_types.h

+6 −1
Original line number Diff line number Diff line
@@ -165,7 +165,12 @@ enum dp_test_pattern { 
	DP_TEST_PATTERN_PRBS23,

	DP_TEST_PATTERN_PRBS31,

	DP_TEST_PATTERN_264BIT_CUSTOM,

	DP_TEST_PATTERN_SQUARE_PULSE,

	DP_TEST_PATTERN_SQUARE_BEGIN,

	DP_TEST_PATTERN_SQUARE = DP_TEST_PATTERN_SQUARE_BEGIN,

	DP_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED,

	DP_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED,

	DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,

	DP_TEST_PATTERN_SQUARE_END = DP_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED,



	/* Link Training Patterns */

	DP_TEST_PATTERN_TRAINING_PATTERN1,