Commit 345c0bc0 authored by Tim Huang's avatar Tim Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add sdma instance check for gfx11 CGCG 



For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,
so not need to configure SDMA1_RLC_CGCG_CTRL for this case.

Signed-off-by: default avatarTim Huang <tim.huang@amd.com>
Reviewed-by: default avatarYifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c10c55cf

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+12 −6
Original line number Diff line number Diff line
@@ -5182,9 +5182,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 
		data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);



		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */

		if (adev->sdma.num_instances > 1) {

			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

			data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);

			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);

		}

	} else {

		/* Program RLC_CGCG_CGLS_CTRL */

		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
@@ -5213,11 +5216,14 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade 
		data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);



		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */

		if (adev->sdma.num_instances > 1) {

			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);

			data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;

			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);

		}

	}

}



static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,

					    bool enable)