Commit 341d2035 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Chen-Yu Tsai
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clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent 



Following what was done on MT8183 and MT8195, also propagate the rate
changes to MFG_BG3D's parent on MT8192 to allow for proper GPU DVFS.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: default avatarChen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220927101128.44758-10-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarChen-Yu Tsai <wenst@chromium.org>
parent 72d38ed7

drivers/clk/mediatek/clk-mt8192-mfg.c

+4 −2
Original line number Diff line number Diff line
@@ -19,7 +19,9 @@ static const struct mtk_gate_regs mfg_cg_regs = { 
};



#define GATE_MFG(_id, _name, _parent, _shift)			\

	GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)

	GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs,	\

		       _shift, &mtk_clk_gate_ops_setclr,	\

		       CLK_SET_RATE_PARENT)



static const struct mtk_gate mfg_clks[] = {

	GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_pll_sel", 0),