Commit 33f85ca4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-05-15' of git://anongit.freedesktop.org/drm/drm 

Pull more drm fixes from Dave Airlie:
 "Looks like I wasn't the only one not fully switched on this week. The
  msm pull has a missing tag so I missed it, and i915 team were a bit
  late. In my defence I did have a day with the roof of my home office
  removed, so was sitting at my kids desk.

  msm:
   - dsi regression fix
   - dma-buf pinning fix
   - displayport fixes
   - llc fix

  i915:
   - Fix active callback alignment annotations and subsequent crashes
   - Retract link training strategy to slow and wide, again
   - Avoid division by zero on gen2
   - Use correct width reads for C0DRB3/C1DRB3 registers
   - Fix double free in pdp allocation failure path
   - Fix HDMI 2.1 PCON downstream caps check"

* tag 'drm-fixes-2021-05-15' of git://anongit.freedesktop.org/drm/drm:
  drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON
  drm/i915/overlay: Fix active retire callback alignment
  drm/i915: Fix crash in auto_retire
  drm/i915/gt: Fix a double free in gen8_preallocate_top_level_pdp
  drm/i915: Read C0DRB3/C1DRB3 as 16 bits again
  drm/i915: Avoid div-by-zero on gen2
  drm/i915/dp: Use slow and wide link training for everything
  drm/msm/dp: initialize audio_comp when audio starts
  drm/msm/dp: check sink_count before update is_connected status
  drm/msm: fix minor version to indicate MSM_PARAM_SUSPENDS support
  drm/msm/dsi: fix msm_dsi_phy_get_clk_provider return code
  drm/msm/dsi: dsi_phy_28nm_8960: fix uninitialized variable access
  drm/msm: fix LLC not being enabled for mmu500 targets
  drm/msm: Do not unpin/evict exported dma-buf's
parents ffb324e6 5dce58de

drivers/gpu/drm/i915/display/intel_dp.c

+6 −55
Original line number Diff line number Diff line
@@ -1095,44 +1095,6 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 
	return -EINVAL;

}



/* Optimize link config in order: max bpp, min lanes, min clock */

static int

intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,

				  struct intel_crtc_state *pipe_config,

				  const struct link_config_limits *limits)

{

	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;

	int bpp, clock, lane_count;

	int mode_rate, link_clock, link_avail;



	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {

		int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);



		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,

						   output_bpp);



		for (lane_count = limits->min_lane_count;

		     lane_count <= limits->max_lane_count;

		     lane_count <<= 1) {

			for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {

				link_clock = intel_dp->common_rates[clock];

				link_avail = intel_dp_max_data_rate(link_clock,

								    lane_count);



				if (mode_rate <= link_avail) {

					pipe_config->lane_count = lane_count;

					pipe_config->pipe_bpp = bpp;

					pipe_config->port_clock = link_clock;



					return 0;

				}

			}

		}

	}



	return -EINVAL;

}



static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)

{

	int i, num_bpc;
@@ -1382,21 +1344,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, 
	    intel_dp_can_bigjoiner(intel_dp))

		pipe_config->bigjoiner = true;



	if (intel_dp_is_edp(intel_dp))

	/*

		 * Optimize for fast and narrow. eDP 1.3 section 3.3 and eDP 1.4

		 * section A.1: "It is recommended that the minimum number of

		 * lanes be used, using the minimum link rate allowed for that

		 * lane configuration."

		 *

		 * Note that we fall back to the max clock and lane count for eDP

		 * panels that fail with the fast optimal settings (see

		 * intel_dp->use_max_params), in which case the fast vs. wide

		 * choice doesn't matter.

	 * Optimize for slow and wide for everything, because there are some

	 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.

	 */

		ret = intel_dp_compute_link_config_fast(intel_dp, pipe_config, &limits);

	else

		/* Optimize for slow and wide. */

	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);



	/* enable compression if the mode doesn't fit available BW */
@@ -2160,7 +2111,7 @@ void intel_dp_check_frl_training(struct intel_dp *intel_dp) 
	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)

	 * -sink is HDMI2.1

	 */

	if (!(intel_dp->dpcd[2] & DP_PCON_SOURCE_CTL_MODE) ||

	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||

	    !intel_dp_is_hdmi_2_1_sink(intel_dp) ||

	    intel_dp->frl.is_trained)

		return;

drivers/gpu/drm/i915/display/intel_overlay.c

+1 −1
Original line number Diff line number Diff line
@@ -383,7 +383,7 @@ static void intel_overlay_off_tail(struct intel_overlay *overlay) 
		i830_overlay_clock_gating(dev_priv, true);

}



static void

__i915_active_call static void

intel_overlay_last_flip_retire(struct i915_active *active)

{

	struct intel_overlay *overlay =

drivers/gpu/drm/i915/gem/i915_gem_mman.c

+1 −1
Original line number Diff line number Diff line
@@ -189,7 +189,7 @@ compute_partial_view(const struct drm_i915_gem_object *obj, 
	struct i915_ggtt_view view;



	if (i915_gem_object_is_tiled(obj))

		chunk = roundup(chunk, tile_row_pages(obj));

		chunk = roundup(chunk, tile_row_pages(obj) ?: 1);



	view.type = I915_GGTT_VIEW_PARTIAL;

	view.partial.offset = rounddown(page_offset, chunk);

drivers/gpu/drm/i915/gt/gen8_ppgtt.c

+0 −1
Original line number Diff line number Diff line
@@ -641,7 +641,6 @@ static int gen8_preallocate_top_level_pdp(struct i915_ppgtt *ppgtt) 


		err = pin_pt_dma(vm, pde->pt.base);

		if (err) {

			i915_gem_object_put(pde->pt.base);

			free_pd(vm, pde);

			return err;

		}

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

+2 −2
Original line number Diff line number Diff line
@@ -653,8 +653,8 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt) 
		 * banks of memory are paired and unswizzled on the

		 * uneven portion, so leave that as unknown.

		 */

		if (intel_uncore_read(uncore, C0DRB3) ==

		    intel_uncore_read(uncore, C1DRB3)) {

		if (intel_uncore_read16(uncore, C0DRB3) ==

		    intel_uncore_read16(uncore, C1DRB3)) {

			swizzle_x = I915_BIT_6_SWIZZLE_9_10;

			swizzle_y = I915_BIT_6_SWIZZLE_9;

		}