Commit 33f2b578 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2023-06-09' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Bit busier and a bit more scattered than usual. amdgpu is the main
  one, with ivpu and msm having a few fixes, then i915, exynos, ast,
  lima, radeon with some misc bits, but overall nothing standing out.

  fb-helper:
   - Fill in fb-helper vars more correctly

  amdgpu:
   - S0ix fixes
   - GPU reset fixes
   - SMU13 fixes
   - SMU11 fixes
   - Misc Display fixes
   - Revert RV/RV2/PCO clock counter changes
   - Fix Stoney xclk value
   - Fix reserved vram debug info

  radeon:
   - Fix a potential use after free

  i915:
   - CDCLK voltage fix for ADL-P
   - eDP wake sync pulse fix
   - Two error handling fixes to selftests

  exynos:
   - Fix wrong return in Exynos vidi driver
   - Fix use-after-free issue to Exynos g2d driver

  ast:
   - resume and modeset fixes for ast

  ivpu:
   - Assorted ivpu fixes

  lima:
   - lima context destroy fix

  msm:
   - Fix max segment size to address splat on newer a6xx
   - Disable PSR by default w/ modparam to re-enable, since there still
     seems to be a lingering issue
   - Fix HPD issue
   - Fix issue with unitialized GMU mutex"

* tag 'drm-fixes-2023-06-09' of git://anongit.freedesktop.org/drm/drm: (32 commits)
  drm/msm/a6xx: initialize GMU mutex earlier
  drm/msm/dp: enable HDP plugin/unplugged interrupts at hpd_enable/disable
  accel/ivpu: Fix sporadic VPU boot failure
  accel/ivpu: Do not use mutex_lock_interruptible
  accel/ivpu: Do not trigger extra VPU reset if the VPU is idle
  drm/amd/display: Reduce sdp bw after urgent to 90%
  drm/amdgpu: change reserved vram info print
  drm/amdgpu: fix xclk freq on CHIP_STONEY
  drm/radeon: fix race condition UAF in radeon_gem_set_domain_ioctl
  Revert "drm/amdgpu: switch to golden tsc registers for raven/raven2"
  Revert "drm/amdgpu: Differentiate between Raven2 and Raven/Picasso according to revision id"
  Revert "drm/amdgpu: change the reference clock for raven/raven2"
  drm/amd/display: add ODM case when looking for first split pipe
  drm/amd: Make lack of `ACPI_FADT_LOW_POWER_S0` or `CONFIG_AMD_PMC` louder during suspend path
  drm/amd/pm: conditionally disable pcie lane switching for some sienna_cichlid SKUs
  drm/amd/pm: Fix power context allocation in SMU13
  drm/amdgpu: fix Null pointer dereference error in amdgpu_device_recover_vram
  drm/amd: Disallow s0ix without BIOS support again
  drm/i915/selftests: Add some missing error propagation
  drm/exynos: fix race condition UAF in exynos_g2d_exec_ioctl
  ...
parents 9cd6357f 986c34b4

drivers/accel/ivpu/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ config DRM_ACCEL_IVPU 
	depends on PCI && PCI_MSI

	select FW_LOADER

	select SHMEM

	select GENERIC_ALLOCATOR

	help

	  Choose this option if you have a system that has an 14th generation Intel CPU

	  or newer. VPU stands for Versatile Processing Unit and it's a CPU-integrated

drivers/accel/ivpu/ivpu_hw_mtl.c

+17 −5
Original line number Diff line number Diff line
@@ -197,6 +197,11 @@ static void ivpu_pll_init_frequency_ratios(struct ivpu_device *vdev) 
	hw->pll.pn_ratio = clamp_t(u8, fuse_pn_ratio, hw->pll.min_ratio, hw->pll.max_ratio);

}



static int ivpu_hw_mtl_wait_for_vpuip_bar(struct ivpu_device *vdev)

{

	return REGV_POLL_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, AON, 0, 100);

}



static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable)

{

	struct ivpu_hw_info *hw = vdev->hw;
@@ -239,6 +244,12 @@ static int ivpu_pll_drive(struct ivpu_device *vdev, bool enable) 
			ivpu_err(vdev, "Timed out waiting for PLL ready status\n");

			return ret;

		}



		ret = ivpu_hw_mtl_wait_for_vpuip_bar(vdev);

		if (ret) {

			ivpu_err(vdev, "Timed out waiting for VPUIP bar\n");

			return ret;

		}

	}



	return 0;
@@ -256,7 +267,7 @@ static int ivpu_pll_disable(struct ivpu_device *vdev) 


static void ivpu_boot_host_ss_rst_clr_assert(struct ivpu_device *vdev)

{

	u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR);

	u32 val = 0;



	val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val);

	val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val);
@@ -754,9 +765,8 @@ static int ivpu_hw_mtl_power_down(struct ivpu_device *vdev) 
{

	int ret = 0;



	if (ivpu_hw_mtl_reset(vdev)) {

	if (!ivpu_hw_mtl_is_idle(vdev) && ivpu_hw_mtl_reset(vdev)) {

		ivpu_err(vdev, "Failed to reset the VPU\n");

		ret = -EIO;

	}



	if (ivpu_pll_disable(vdev)) {
@@ -764,8 +774,10 @@ static int ivpu_hw_mtl_power_down(struct ivpu_device *vdev) 
		ret = -EIO;

	}



	if (ivpu_hw_mtl_d0i3_enable(vdev))

		ivpu_warn(vdev, "Failed to enable D0I3\n");

	if (ivpu_hw_mtl_d0i3_enable(vdev)) {

		ivpu_err(vdev, "Failed to enter D0I3\n");

		ret = -EIO;

	}



	return ret;

}

drivers/accel/ivpu/ivpu_hw_mtl_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -91,6 +91,7 @@ 
#define MTL_VPU_HOST_SS_CPR_RST_SET_MSS_MAS_MASK			BIT_MASK(11)



#define MTL_VPU_HOST_SS_CPR_RST_CLR					0x00000098u

#define MTL_VPU_HOST_SS_CPR_RST_CLR_AON_MASK				BIT_MASK(0)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_TOP_NOC_MASK			BIT_MASK(1)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_DSS_MAS_MASK			BIT_MASK(10)

#define MTL_VPU_HOST_SS_CPR_RST_CLR_MSS_MAS_MASK			BIT_MASK(11)

drivers/accel/ivpu/ivpu_ipc.c

+1 −3
Original line number Diff line number Diff line
@@ -183,9 +183,7 @@ ivpu_ipc_send(struct ivpu_device *vdev, struct ivpu_ipc_consumer *cons, struct v 
	struct ivpu_ipc_info *ipc = vdev->ipc;

	int ret;



	ret = mutex_lock_interruptible(&ipc->lock);

	if (ret)

		return ret;

	mutex_lock(&ipc->lock);



	if (!ipc->on) {

		ret = -EAGAIN;

drivers/accel/ivpu/ivpu_job.c

+14 −7
Original line number Diff line number Diff line
@@ -431,6 +431,7 @@ ivpu_job_prepare_bos_for_submit(struct drm_file *file, struct ivpu_job *job, u32 
	struct ivpu_file_priv *file_priv = file->driver_priv;

	struct ivpu_device *vdev = file_priv->vdev;

	struct ww_acquire_ctx acquire_ctx;

	enum dma_resv_usage usage;

	struct ivpu_bo *bo;

	int ret;

	u32 i;
@@ -461,22 +462,28 @@ ivpu_job_prepare_bos_for_submit(struct drm_file *file, struct ivpu_job *job, u32 


	job->cmd_buf_vpu_addr = bo->vpu_addr + commands_offset;



	ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);

	ret = drm_gem_lock_reservations((struct drm_gem_object **)job->bos, buf_count,

					&acquire_ctx);

	if (ret) {

		ivpu_warn(vdev, "Failed to lock reservations: %d\n", ret);

		return ret;

	}



	ret = dma_resv_reserve_fences(bo->base.resv, 1);

	for (i = 0; i < buf_count; i++) {

		ret = dma_resv_reserve_fences(job->bos[i]->base.resv, 1);

		if (ret) {

			ivpu_warn(vdev, "Failed to reserve fences: %d\n", ret);

			goto unlock_reservations;

		}

	}



	dma_resv_add_fence(bo->base.resv, job->done_fence, DMA_RESV_USAGE_WRITE);

	for (i = 0; i < buf_count; i++) {

		usage = (i == CMD_BUF_IDX) ? DMA_RESV_USAGE_WRITE : DMA_RESV_USAGE_BOOKKEEP;

		dma_resv_add_fence(job->bos[i]->base.resv, job->done_fence, usage);

	}



unlock_reservations:

	drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, 1, &acquire_ctx);

	drm_gem_unlock_reservations((struct drm_gem_object **)job->bos, buf_count, &acquire_ctx);



	wmb(); /* Flush write combining buffers */